Skip to content

GitLab

Commit d4ad3da0 authored by Varun Wadekar's avatar Varun Wadekar
Browse files

refactor(tegra132): deprecate platform 



The Tegra132 platforms have reached their end of life and are
no longer used in the field. Internally and externally, all
known programs have removed support for this legacy platform.

This change removes this platform from the Tegra tree as a result.
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
Change-Id: I72edb689293e23b63290cdcaef60468b90687a5a
parent 485d1f80
Hide whitespace changes
Inline Side-by-side
docs/plat/nvidia-tegra.rst
View file @ d4ad3da0
...@@ -19,7 +19,7 @@ The NVIDIA® Parker (T186) series system-on-chip (SoC) delivers a heterogeneous ...@@ -19,7 +19,7 @@ The NVIDIA® Parker (T186) series system-on-chip (SoC) delivers a heterogeneous
multi-processing (HMP) solution designed to optimize performance and multi-processing (HMP) solution designed to optimize performance and
efficiency. efficiency.
T186 has Dual NVIDIA Denver 2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores, T186 has Dual NVIDIA Denver2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
including legacy ARMv7 applications. The Denver 2 processors each have 128 KB including legacy ARMv7 applications. The Denver 2 processors each have 128 KB
...@@ -29,20 +29,6 @@ Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A ...@@ -29,20 +29,6 @@ Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A
high speed coherency fabric connects these two processor complexes and allows high speed coherency fabric connects these two processor complexes and allows
heterogeneous multi-processing with all six cores if required. heterogeneous multi-processing with all six cores if required.
- .. rubric:: T210
:name: t210
T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
including legacy Armv7-A applications. The Cortex-A57 processors each have
48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
- .. rubric:: T132
:name: t132
Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
fully Armv8-A architecture compatible. Each of the two Denver cores fully Armv8-A architecture compatible. Each of the two Denver cores
implements a 7-way superscalar microarchitecture (up to 7 concurrent implements a 7-way superscalar microarchitecture (up to 7 concurrent
...@@ -68,6 +54,17 @@ Denver also features new low latency power-state transitions, in addition ...@@ -68,6 +54,17 @@ Denver also features new low latency power-state transitions, in addition
to extensive power-gating and dynamic voltage and clock scaling based on to extensive power-gating and dynamic voltage and clock scaling based on
workloads. workloads.
- .. rubric:: T210
:name: t210
T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
including legacy Armv7-A applications. The Cortex-A57 processors each have
48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
Directory structure Directory structure
------------------- -------------------
...@@ -89,7 +86,6 @@ their dispatchers in the image without changing any makefiles. ...@@ -89,7 +86,6 @@ their dispatchers in the image without changing any makefiles.
These are the supported Trusted OS' by Tegra platforms. These are the supported Trusted OS' by Tegra platforms.
- Tegra132: TLK
- Tegra210: TLK and Trusty - Tegra210: TLK and Trusty
- Tegra186: Trusty - Tegra186: Trusty
- Tegra194: Trusty - Tegra194: Trusty
...@@ -110,7 +106,7 @@ Preparing the BL31 image to run on Tegra SoCs ...@@ -110,7 +106,7 @@ Preparing the BL31 image to run on Tegra SoCs
.. code:: shell .. code:: shell
CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \ CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
TARGET_SOC=<target-soc e.g. t194|t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd> TARGET_SOC=<target-soc e.g. t194|t186|t210> SPD=<dispatcher e.g. trusty|tlkd>
bl31 bl31
Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>`` Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>``
......
plat/nvidia/tegra/common/tegra_platform.c
View file @ d4ad3da0
/* /*
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -82,13 +82,6 @@ static uint32_t tegra_get_chipid_pre_si_platform(void) ...@@ -82,13 +82,6 @@ static uint32_t tegra_get_chipid_pre_si_platform(void)
return (tegra_get_chipid() >> PRE_SI_PLATFORM_SHIFT) & PRE_SI_PLATFORM_MASK; return (tegra_get_chipid() >> PRE_SI_PLATFORM_SHIFT) & PRE_SI_PLATFORM_MASK;
} }
bool tegra_chipid_is_t132(void)
{
uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
return (chip_id == TEGRA_CHIPID_TEGRA13);
}
bool tegra_chipid_is_t186(void) bool tegra_chipid_is_t186(void)
{ {
uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK; uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
......
plat/nvidia/tegra/include/t132/tegra_def.h deleted 100644 → 0
View file @ 485d1f80
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef TEGRA_DEF_H
#define TEGRA_DEF_H
#include <lib/utils_def.h>
/*******************************************************************************
* Platform BL31 specific defines.
******************************************************************************/
#define BL31_SIZE U(0x40000)
/*******************************************************************************
* This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
* call as the `state-id` field in the 'power state' parameter.
******************************************************************************/
#define PSTATE_ID_SOC_POWERDN U(0xD)
/*******************************************************************************
* Platform power states (used by PSCI framework)
*
* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
******************************************************************************/
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
/*******************************************************************************
* Chip specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
/*******************************************************************************
* GIC memory map
******************************************************************************/
#define TEGRA_GICD_BASE U(0x50041000)
#define TEGRA_GICC_BASE U(0x50042000)
/*******************************************************************************
* Tegra micro-seconds timer constants
******************************************************************************/
#define TEGRA_TMRUS_BASE U(0x60005010)
#define TEGRA_TMRUS_SIZE U(0x1000)
/*******************************************************************************
* Tegra Clock and Reset Controller constants
******************************************************************************/
#define TEGRA_CAR_RESET_BASE U(0x60006000)
#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
#define GPU_RESET_BIT (U(1) << 24)
#define GPU_SET_BIT (U(1) << 24)
/*******************************************************************************
* Tegra Flow Controller constants
******************************************************************************/
#define TEGRA_FLOWCTRL_BASE U(0x60007000)
/*******************************************************************************
* Tegra Secure Boot Controller constants
******************************************************************************/
#define TEGRA_SB_BASE U(0x6000C200)
/*******************************************************************************
* Tegra Exception Vectors constants
******************************************************************************/
#define TEGRA_EVP_BASE U(0x6000F000)
/*******************************************************************************
* Tegra Miscellaneous register constants
******************************************************************************/
#define TEGRA_MISC_BASE U(0x70000000)
#define HARDWARE_REVISION_OFFSET U(0x804)
/*******************************************************************************
* Tegra UART controller base addresses
******************************************************************************/
#define TEGRA_UARTA_BASE U(0x70006000)
#define TEGRA_UARTB_BASE U(0x70006040)
#define TEGRA_UARTC_BASE U(0x70006200)
#define TEGRA_UARTD_BASE U(0x70006300)
#define TEGRA_UARTE_BASE U(0x70006400)
/*******************************************************************************
* Tegra Power Mgmt Controller constants
******************************************************************************/
#define TEGRA_PMC_BASE U(0x7000E400)
/*******************************************************************************
* Tegra Memory Controller constants
******************************************************************************/
#define TEGRA_MC_BASE U(0x70019000)
/* Memory Controller Interrupt Status */
#define MC_INTSTATUS 0x00U
/* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 U(0x70)
#define MC_SECURITY_CFG1_0 U(0x74)
#define MC_SECURITY_CFG3_0 U(0x9BC)
/* Video Memory carveout configuration registers */
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
/*******************************************************************************
* Tegra TZRAM constants
******************************************************************************/
#define TEGRA_TZRAM_BASE U(0x7C010000)
#define TEGRA_TZRAM_SIZE U(0x10000)
/*******************************************************************************
* Tegra DRAM memory base address
******************************************************************************/
#define TEGRA_DRAM_BASE ULL(0x80000000)
#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
#endif /* TEGRA_DEF_H */
plat/nvidia/tegra/include/tegra_platform.h
View file @ d4ad3da0
/* /*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -49,7 +49,6 @@ uint32_t tegra_get_chipid_minor(void); ...@@ -49,7 +49,6 @@ uint32_t tegra_get_chipid_minor(void);
/* /*
* Tegra chip ID identifiers * Tegra chip ID identifiers
*/ */
bool tegra_chipid_is_t132(void);
bool tegra_chipid_is_t186(void); bool tegra_chipid_is_t186(void);
bool tegra_chipid_is_t210(void); bool tegra_chipid_is_t210(void);
bool tegra_chipid_is_t210_b01(void); bool tegra_chipid_is_t210_b01(void);
......
plat/nvidia/tegra/soc/t132/plat_psci_handlers.c deleted 100644 → 0
View file @ 485d1f80
/*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <platform_def.h>
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <denver.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <flowctrl.h>
#include <pmc.h>
#include <tegra_def.h>
#include <tegra_private.h>
/*
* Register used to clear CPU reset signals. Each CPU has two reset
* signals: CPU reset (3:0) and Core reset (19:16)
*/
#define CPU_CMPLX_RESET_CLR 0x344
#define CPU_CORE_RESET_MASK 0x10001
/* Clock and Reset controller registers for system clock's settings */
#define SCLK_RATE 0x30
#define SCLK_BURST_POLICY 0x28
#define SCLK_BURST_POLICY_DEFAULT 0x10000000
static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
const plat_local_state_t *states,
uint32_t ncpu)
{
plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
uint32_t num_cpu = ncpu;
const plat_local_state_t *local_state = states;
(void)lvl;
assert(ncpu != 0U);
do {
temp = *local_state;
if ((temp < target)) {
target = temp;
}
--num_cpu;
local_state++;
} while (num_cpu != 0U);
return target;
}
int32_t tegra_soc_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
int state_id = psci_get_pstate_id(power_state);
int cpu = read_mpidr() & MPIDR_CPU_MASK;
/*
* Sanity check the requested state id, power level and CPU number.
* Currently T132 only supports SYSTEM_SUSPEND on last standing CPU
* i.e. CPU 0
*/
if ((state_id != PSTATE_ID_SOC_POWERDN) || (cpu != 0)) {
ERROR("unsupported state id @ power level\n");
return PSCI_E_INVALID_PARAMS;
}
/* Set lower power states to PLAT_MAX_OFF_STATE */
for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
/* Set the SYSTEM_SUSPEND state-id */
req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
PSTATE_ID_SOC_POWERDN;
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_on(u_register_t mpidr)
{
int cpu = mpidr & MPIDR_CPU_MASK;
uint32_t mask = CPU_CORE_RESET_MASK << cpu;
if (cpu_powergate_mask[cpu] == 0) {
/* Deassert CPU reset signals */
mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
/* Power on CPU using PMC */
tegra_pmc_cpu_on(cpu);
/* Fill in the CPU powergate mask */
cpu_powergate_mask[cpu] = 1;
} else {
/* Power on CPU using Flow Controller */
tegra_fc_cpu_on(cpu);
}
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
/*
* Lock scratch registers which hold the CPU vectors
*/
tegra_pmc_lock_cpu_vectors();
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
{
uint64_t val;
tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
/* Disable DCO operations */
denver_disable_dco();
/* Power down the CPU */
val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
write_actlr_el1(val | DENVER_CPU_STATE_POWER_DOWN);
return PSCI_E_SUCCESS;
}
int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
{
(void)cpu_state;
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
{
uint64_t val;
#if ENABLE_ASSERTIONS
int cpu = read_mpidr() & MPIDR_CPU_MASK;
/* SYSTEM_SUSPEND only on CPU0 */
assert(cpu == 0);
#endif
/* Allow restarting CPU #1 using PMC on suspend exit */
cpu_powergate_mask[1] = 0;
/* Program FC to enter suspend state */
tegra_fc_cpu_powerdn(read_mpidr());
/* Disable DCO operations */
denver_disable_dco();
/* Program the suspend state ID */
val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
write_actlr_el1(val | target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
return PSCI_E_SUCCESS;
}
int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
{
return PSCI_E_NOT_SUPPORTED;
}
int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
{
return PSCI_E_SUCCESS;
}
int tegra_soc_prepare_system_reset(void)
{
/*
* Set System Clock (SCLK) to POR default so that the clock source
* for the PMC APB clock would not be changed due to system reset.
*/
mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY,
SCLK_BURST_POLICY_DEFAULT);
mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0);
/* Wait 1 ms to make sure clock source/device logic is stabilized. */
mdelay(1);
/*
* Program the PMC in order to restart the system.
*/
tegra_pmc_system_reset();
return PSCI_E_SUCCESS;
}
__dead2 void tegra_soc_prepare_system_off(void)
{
ERROR("Tegra System Off: operation not handled.\n");
panic();
}
plat/nvidia/tegra/soc/t132/plat_secondary.c deleted 100644 → 0
View file @ 485d1f80
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <denver.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
#include <pmc.h>
#include <tegra_def.h>
#define SB_CSR 0x0
#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1)
/* AARCH64 CPU reset vector */
#define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */
#define SB_AA64_RESET_HI 0x34 /* width = 11:0 */
/* AARCH32 CPU reset vector */
#define EVP_CPU_RESET_VECTOR 0x100
extern void tegra_secure_entrypoint(void);
/*
* For T132, CPUs reset to AARCH32, so the reset vector is first
* armv8_trampoline which does a warm reset to AARCH64 and starts
* execution at the address in SB_AA64_RESET_LOW/SB_AA64_RESET_HI.
*/
__aligned(8) const uint32_t armv8_trampoline[] = {
0xE3A00003, /* mov r0, #3 */
0xEE0C0F50, /* mcr p15, 0, r0, c12, c0, 2 */
0xEAFFFFFE, /* b . */
};
/*******************************************************************************
* Setup secondary CPU vectors
******************************************************************************/
void plat_secondary_setup(void)
{
uint32_t val;
uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint;
/*
* For T132, CPUs reset to AARCH32, so the reset vector is first
* armv8_trampoline, which does a warm reset to AARCH64 and starts
* execution at the address in SCRATCH34/SCRATCH35.
*/
INFO("Setting up T132 CPU boot\n");
/* initial AARCH32 reset address */
tegra_pmc_write_32(PMC_SECURE_SCRATCH22,
(unsigned long)&armv8_trampoline);
/* set AARCH32 exception vector (read to flush) */
mmio_write_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR,
(unsigned long)&armv8_trampoline);
val = mmio_read_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR);
/* setup secondary CPU vector */
mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW,
(reset_addr & 0xFFFFFFFF) | 1);
val = reset_addr >> 32;
mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF);
/* configure PMC */
tegra_pmc_cpu_setup(reset_addr);
tegra_pmc_lock_cpu_vectors();
}
plat/nvidia/tegra/soc/t132/plat_setup.c deleted 100644 → 0
View file @ 485d1f80
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <assert.h>
#include <common/bl_common.h>
#include <drivers/console.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <memctrl.h>
#include <plat/common/platform.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
/* sets of MMIO ranges setup */
#define MMIO_RANGE_0_ADDR 0x50000000
#define MMIO_RANGE_1_ADDR 0x60000000
#define MMIO_RANGE_2_ADDR 0x70000000
#define MMIO_RANGE_SIZE 0x200000
/*
* Table of regions to map using the MMU.
*/
static const mmap_region_t tegra_mmap[] = {
MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
{0}
};
/*******************************************************************************
* Set up the pagetables as per the platform memory map & initialize the MMU
******************************************************************************/
const mmap_region_t *plat_get_mmio_map(void)
{
/* MMIO space */
return tegra_mmap;
}
/*******************************************************************************
* The Tegra power domain tree has a single system level power domain i.e. a
* single root node. The first entry in the power domain descriptor specifies
* the number of power domains at the highest power level.
*******************************************************************************
*/
const unsigned char tegra_power_domain_tree_desc[] = {
/* No of root nodes */
1,
/* No of clusters */
PLATFORM_CLUSTER_COUNT,
/* No of CPU cores */
PLATFORM_CORE_COUNT,
};
/*******************************************************************************
* This function returns the Tegra default topology tree information.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
{
return tegra_power_domain_tree_desc;
}
unsigned int plat_get_syscnt_freq2(void)
{
return 12000000;
}
/*******************************************************************************
* Maximum supported UART controllers
******************************************************************************/
#define TEGRA132_MAX_UART_PORTS 5
/*******************************************************************************
* This variable holds the UART port base addresses
******************************************************************************/
static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
0, /* undefined - treated as an error case */
TEGRA_UARTA_BASE,
TEGRA_UARTB_BASE,
TEGRA_UARTC_BASE,
TEGRA_UARTD_BASE,
TEGRA_UARTE_BASE,
};
/*******************************************************************************
* Enable console corresponding to the console ID
******************************************************************************/
void plat_enable_console(int32_t id)
{
static console_t uart_console;
uint32_t console_clock;
if ((id > 0) && (id < TEGRA132_MAX_UART_PORTS)) {
/*
* Reference clock used by the FPGAs is a lot slower.
*/
if (tegra_platform_is_fpga()) {
console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
} else {
console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
}
(void)console_16550_register(tegra132_uart_addresses[id],
console_clock,
TEGRA_CONSOLE_BAUDRATE,
&uart_console);
console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
}
}
/*******************************************************************************
* Initialize the GIC and SGIs
******************************************************************************/
void plat_gic_setup(void)
{
tegra_gic_setup(NULL, 0);
tegra_gic_init();
}
/*******************************************************************************
* Return pointer to the BL31 params from previous bootloader
******************************************************************************/
struct tegra_bl31_params *plat_get_bl31_params(void)
{
return NULL;
}
/*******************************************************************************
* Return pointer to the BL31 platform params from previous bootloader
******************************************************************************/
plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
{
return NULL;
}
/*******************************************************************************
* Handler for early platform setup
******************************************************************************/
void plat_early_platform_setup(void)
{
plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
/* Verify chip id is t132 */
assert(tegra_chipid_is_t132());
/*
* Do initial security configuration to allow DRAM/device access.
*/
tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
(uint32_t)plat_params->tzdram_size);
}
/*******************************************************************************
* Handler for late platform setup
******************************************************************************/
void plat_late_platform_setup(void)
{
; /* do nothing */
}
/*******************************************************************************
* Handler to indicate support for System Suspend
******************************************************************************/
bool plat_supports_system_suspend(void)
{
return true;
}
/*******************************************************************************
* Platform specific runtime setup.
******************************************************************************/
void plat_runtime_setup(void)
{
/*
* During cold boot, it is observed that the arbitration
* bit is set in the Memory controller leading to false
* error interrupts in the non-secure world. To avoid
* this, clean the interrupt status register before
* booting into the non-secure world
*/
tegra_memctrl_clear_pending_interrupts();
/*
* During boot, USB3 and flash media (SDMMC/SATA) devices need
* access to IRAM. Because these clients connect to the MC and
* do not have a direct path to the IRAM, the MC implements AHB
* redirection during boot to allow path to IRAM. In this mode
* accesses to a programmed memory address aperture are directed
* to the AHB bus, allowing access to the IRAM. This mode must be
* disabled before we jump to the non-secure world.
*/
tegra_memctrl_disable_ahb_redirection();
}
plat/nvidia/tegra/soc/t132/plat_sip_calls.c deleted 100644 → 0
View file @ 485d1f80
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <arch.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <tegra_private.h>
#define NS_SWITCH_AARCH32 1
#define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT)
/*******************************************************************************
* Tegra132 SiP SMCs
******************************************************************************/
#define TEGRA_SIP_AARCH_SWITCH 0x82000004
/*******************************************************************************
* SPSR settings for AARCH32/AARCH64 modes
******************************************************************************/
#define SPSR32 SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, \
DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT)
#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)
/*******************************************************************************
* This function is responsible for handling all T132 SiP calls
******************************************************************************/
int plat_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
const void *cookie,
void *handle,
uint64_t flags)
{
switch (smc_fid) {
case TEGRA_SIP_AARCH_SWITCH:
/* clean up the high bits */
x1 = (uint32_t)x1;
x2 = (uint32_t)x2;
if (!x1 || x2 > NS_SWITCH_AARCH32) {
ERROR("%s: invalid parameters\n", __func__);
return -EINVAL;
}
/* x1 = ns entry point */
cm_set_elr_spsr_el3(NON_SECURE, x1,
(x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64);
/* switch NS world mode */
cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2);
INFO("CPU switched to AARCH%s mode\n",
(x2 == NS_SWITCH_AARCH32) ? "32" : "64");
return 0;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;
}
return -ENOTSUP;
}
plat/nvidia/tegra/soc/t132/platform_t132.mk deleted 100644 → 0
View file @ 485d1f80
#
# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
TZDRAM_BASE := 0xF5C00000
$(eval $(call add_define,TZDRAM_BASE))
PLATFORM_CLUSTER_COUNT := 1
$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
PLATFORM_MAX_CPUS_PER_CLUSTER := 2
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
MAX_XLAT_TABLES := 3
$(eval $(call add_define,MAX_XLAT_TABLES))
MAX_MMAP_REGIONS := 8
$(eval $(call add_define,MAX_MMAP_REGIONS))
# platform files
PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t132
BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
${TEGRA_DRIVERS}/flowctrl/flowctrl.c \
${TEGRA_DRIVERS}/memctrl/memctrl_v1.c \
${TEGRA_DRIVERS}/pmc/pmc.c \
${SOC_DIR}/plat_psci_handlers.c \
${SOC_DIR}/plat_sip_calls.c \
${SOC_DIR}/plat_setup.c \
${SOC_DIR}/plat_secondary.c
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment