Merge changes I5693ad56,I9ddc077a into integration

* changes:
  mediatek: mt8183: Fix AARCH64 init fail on CPU0
  mediatek: mt8183: refine GIC driver for low power scenarios

plat/mediatek/mt8183/include/mt_gic_v3.h

@@ -15,15 +15,19 @@
 #define GIC500_ACTIVE_CPU_SHIFT 16
 #define GIC500_ACTIVE_CPU_MASK (0xff << GIC500_ACTIVE_CPU_SHIFT)
 
+#define NR_INT_POL_CTL 20
+
 void mt_gic_driver_init(void);
 void mt_gic_init(void);
 void mt_gic_set_pending(uint32_t irq);
 uint32_t mt_gic_get_pending(uint32_t irq);
 void mt_gic_cpuif_enable(void);
 void mt_gic_cpuif_disable(void);
-void mt_gic_pcpu_init(void);
-void mt_gic_irq_save(void);
-void mt_gic_irq_restore(void);
+void mt_gic_rdistif_init(void);
+void mt_gic_distif_save(void);
+void mt_gic_distif_restore(void);
+void mt_gic_rdistif_save(void);
+void mt_gic_rdistif_restore(void);
 void mt_gic_sync_dcm_enable(void);
 void mt_gic_sync_dcm_disable(void);
 

plat/mediatek/mt8183/plat_mt_gic.c

@@ -11,18 +11,17 @@
 #include <bl31/interrupt_mgmt.h>
 #include <mt_gic_v3.h>
 #include <mtk_plat_common.h>
+#include "../drivers/arm/gic/v3/gicv3_private.h"
 #include "plat_private.h"
 #include <plat/common/platform.h>
 #include <platform_def.h>
 #include <stdint.h>
 #include <stdio.h>
 
-#define NR_INT_POL_CTL         20
-
 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT];
 
 /* we save and restore the GICv3 context on system suspend */
-gicv3_redist_ctx_t rdist_ctx;
 gicv3_dist_ctx_t dist_ctx;
 
 static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
@@ -38,6 +37,16 @@ gicv3_driver_data_t mt_gicv3_data = {
 	.mpidr_to_core_pos = mt_mpidr_to_core_pos,
 };
 
+struct gic_chip_data {
+	unsigned int saved_group;
+	unsigned int saved_enable;
+	unsigned int saved_conf0;
+	unsigned int saved_conf1;
+	unsigned int saved_grpmod;
+};
+
+static struct gic_chip_data gic_data;
+
 void clear_sec_pol_ctl_en(void)
 {
 	unsigned int i;
@@ -54,15 +63,6 @@ void mt_gic_driver_init(void)
 	gicv3_driver_init(&mt_gicv3_data);
 }
 
-void mt_gic_init(void)
-{
-	gicv3_distif_init();
-	gicv3_rdistif_init(plat_my_core_pos());
-	gicv3_cpuif_enable(plat_my_core_pos());
-
-	clear_sec_pol_ctl_en();
-}
-
 void mt_gic_set_pending(uint32_t irq)
 {
 	gicv3_set_interrupt_pending(irq, plat_my_core_pos());
@@ -78,35 +78,83 @@ void mt_gic_cpuif_disable(void)
 	gicv3_cpuif_disable(plat_my_core_pos());
 }
 
-void mt_gic_pcpu_init(void)
+void mt_gic_rdistif_init(void)
 {
-	gicv3_rdistif_init(plat_my_core_pos());
+	unsigned int proc_num;
+	unsigned int index;
+	uintptr_t gicr_base;
+
+	proc_num = plat_my_core_pos();
+	gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+
+	/* set all SGI/PPI as non-secure GROUP1 by default */
+	mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U);
+	mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0);
+
+	/* setup the default PPI/SGI priorities */
+	for (index = 0; index < TOTAL_PCPU_INTR_NUM; index += 4U)
+		gicr_write_ipriorityr(gicr_base, index,
+				GICD_IPRIORITYR_DEF_VAL);
 }
 
-void mt_gic_irq_save(void)
+void mt_gic_distif_save(void)
 {
-	gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
 	gicv3_distif_save(&dist_ctx);
 }
 
-void mt_gic_irq_restore(void)
+void mt_gic_distif_restore(void)
 {
 	gicv3_distif_init_restore(&dist_ctx);
-	gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
 }
 
-void mt_gic_sync_dcm_enable(void)
+void mt_gic_rdistif_save(void)
 {
-	unsigned int val = mmio_read_32(GIC_SYNC_DCM);
+	unsigned int proc_num;
+	uintptr_t gicr_base;
+
+	proc_num = plat_my_core_pos();
+	gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
 
-	val &= ~GIC_SYNC_DCM_MASK;
-	mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_ON);
+	gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0);
+	gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0);
+	gic_data.saved_conf0 = mmio_read_32(gicr_base + GICR_ICFGR0);
+	gic_data.saved_conf1 = mmio_read_32(gicr_base + GICR_ICFGR1);
+	gic_data.saved_grpmod = mmio_read_32(gicr_base + GICR_IGRPMODR0);
+
+	rdist_has_saved[proc_num] = 1;
+}
+
+void mt_gic_rdistif_restore(void)
+{
+	unsigned int proc_num;
+	uintptr_t gicr_base;
+
+	proc_num = plat_my_core_pos();
+	if (rdist_has_saved[proc_num] == 1) {
+		gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+		mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group);
+		mmio_write_32(gicr_base + GICR_ISENABLER0, gic_data.saved_enable);
+		mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0);
+		mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1);
+		mmio_write_32(gicr_base + GICR_IGRPMODR0, gic_data.saved_grpmod);
+	}
+}
+
+void mt_gic_sync_dcm_enable(void)
+{
+	mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_ON);
 }
 
 void mt_gic_sync_dcm_disable(void)
 {
-	unsigned int val = mmio_read_32(GIC_SYNC_DCM);
+	mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_OFF);
+}
+
+void mt_gic_init(void)
+{
+	gicv3_distif_init();
+	gicv3_cpuif_enable(plat_my_core_pos());
+	mt_gic_rdistif_init();
 
-	val &= ~GIC_SYNC_DCM_MASK;
-	mmio_write_32(GIC_SYNC_DCM, val | GIC_SYNC_DCM_OFF);
+	clear_sec_pol_ctl_en();
 }

plat/mediatek/mt8183/plat_pm.c

@@ -152,6 +152,21 @@ static bool clst_single_on(int cluster, int cpu)
 	return !(on_stat & (cpu_mask[cluster] & ~BIT(my_idx)));
 }
 
+static void plat_cpu_pwrdwn_common(void)
+{
+	/* Prevent interrupts from spuriously waking up this cpu */
+	mt_gic_rdistif_save();
+	mt_gic_cpuif_disable();
+}
+
+static void plat_cpu_pwron_common(void)
+{
+	/* Enable the gic cpu interface */
+	mt_gic_cpuif_enable();
+	mt_gic_rdistif_init();
+	mt_gic_rdistif_restore();
+}
+
 static void plat_cluster_pwrdwn_common(uint64_t mpidr, int cluster)
 {
 	if (cluster > 0)
@@ -289,13 +304,19 @@ static int plat_mtk_power_domain_on(unsigned long mpidr)
 {
 	int cpu = MPIDR_AFFLVL0_VAL(mpidr);
 	int cluster = MPIDR_AFFLVL1_VAL(mpidr);
+	int clst_pwr = spm_get_cluster_powerstate(cluster);
+	unsigned int i;
 
 	mcdi_ctrl_before_hotplug_on(cluster, cpu);
 	hotplug_ctrl_cluster_on(cluster, cpu);
 
-	/* init cpu reset arch as AARCH64 */
-	mcucfg_init_archstate(cluster, cpu, 1);
-	mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
+	if (clst_pwr == 0) {
+		/* init cpu reset arch as AARCH64 of cluster */
+		for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) {
+			mcucfg_init_archstate(cluster, i, 1);
+			mcucfg_set_bootaddr(cluster, i, secure_entrypoint);
+		}
+	}
 
 	hotplug_ctrl_cpu_on(cluster, cpu);
 
@@ -312,7 +333,7 @@ static void plat_mtk_power_domain_off(const psci_power_state_t *state)
 	bool cluster_off = (HP_CLUSTER_OFF && afflvl1 &&
 					clst_single_on(cluster, cpu));
 
-	mt_gic_cpuif_disable();
+	plat_cpu_pwrdwn_common();
 
 	if (cluster_off)
 		plat_cluster_pwrdwn_common(mpidr, cluster);
@@ -332,8 +353,7 @@ static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state)
 	if (afflvl1)
 		plat_cluster_pwron_common(mpidr, cluster);
 
-	mt_gic_pcpu_init();
-	mt_gic_cpuif_enable();
+	plat_cpu_pwron_common();
 
 	hotplug_ctrl_cpu_on_finish(cluster, cpu);
 }
@@ -348,12 +368,8 @@ static void plat_mtk_power_domain_suspend(const psci_power_state_t *state)
 	bool afflvl2 = (pds[MPIDR_AFFLVL2] == MTK_LOCAL_STATE_OFF);
 	bool cluster_off = MCDI_C2 && afflvl1 && clst_single_pwr(cluster, cpu);
 
-	/* init cpu reset arch as AARCH64 */
-	mcucfg_init_archstate(cluster, cpu, 1);
-	mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
+	plat_cpu_pwrdwn_common();
 
-	mt_gic_cpuif_disable();
-	mt_gic_irq_save();
 	plat_dcm_mcsi_a_backup();
 
 	if (cluster_off || afflvl2)
@@ -376,6 +392,8 @@ static void plat_mtk_power_domain_suspend(const psci_power_state_t *state)
 		if (MCDI_SSPM)
 			while (sspm_ipi_recv_non_blocking(IPI_ID_SUSPEND, d, l))
 				;
+
+		mt_gic_distif_save();
 	} else {
 		mcdi_ctrl_cluster_cpu_off(cluster, cpu, cluster_off);
 	}
@@ -394,7 +412,9 @@ static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state
 		uint32_t l = sizeof(spm_d) / sizeof(uint32_t);
 
 		mt_gic_init();
-		mt_gic_irq_restore();
+		mt_gic_distif_restore();
+		mt_gic_rdistif_restore();
+
 		mmio_write_32(EMI_WFIFO, 0xf);
 
 		if (MCDI_SSPM)
@@ -407,6 +427,8 @@ static void plat_mtk_power_domain_suspend_finish(const psci_power_state_t *state
 				;
 
 		mcdi_ctrl_resume();
+	} else {
+		plat_cpu_pwron_common();
 	}
 
 	plat_cluster_pwron_common(mpidr, cluster);
@@ -541,15 +563,23 @@ static const plat_psci_ops_t plat_plat_pm_ops = {
 	.system_off			= plat_mtk_system_off,
 	.system_reset			= plat_mtk_system_reset,
 	.validate_power_state		= plat_mtk_validate_power_state,
-	.get_sys_suspend_power_state	= plat_mtk_get_sys_suspend_power_state,
+	.get_sys_suspend_power_state	= plat_mtk_get_sys_suspend_power_state
 };
 
 int plat_setup_psci_ops(uintptr_t sec_entrypoint,
 			const plat_psci_ops_t **psci_ops)
 {
+	unsigned int i;
+
 	*psci_ops = &plat_plat_pm_ops;
 	secure_entrypoint = sec_entrypoint;
 
+	/* Init cpu reset arch as AARCH64 of cluster 0 */
+	for (i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER; i++) {
+		mcucfg_init_archstate(0, i, 1);
+		mcucfg_set_bootaddr(0, i, secure_entrypoint);
+	}
+
 	if (!check_mcdi_ctl_stat()) {
 		HP_SSPM_CTRL = false;
 		MCDI_SSPM = false;