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Commit d6845d3d authored by davidcunado-arm's avatar davidcunado-arm Committed by GitHub
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Merge pull request #835 from rockchip-linux/rk3399-atf-cleanup-20170210 

RK3399 ARM TF clean up 20170210
parents 86a3b266 ccdc044a
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plat/rockchip/common/include/plat_private.h
View file @ d6845d3d
...@@ -44,6 +44,7 @@ ...@@ -44,6 +44,7 @@
extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
extern uint32_t __sram_incbin_start, __sram_incbin_end;
/****************************************************************************** /******************************************************************************
* For rockchip socs pm ops * For rockchip socs pm ops
......
plat/rockchip/common/pmusram/pmu_sram.c
View file @ d6845d3d
...@@ -62,6 +62,12 @@ void rockchip_plat_sram_mmu_el3(void) ...@@ -62,6 +62,12 @@ void rockchip_plat_sram_mmu_el3(void)
mmap_add_region((unsigned long)&__bl31_sram_data_start, mmap_add_region((unsigned long)&__bl31_sram_data_start,
(unsigned long)&__bl31_sram_data_start, (unsigned long)&__bl31_sram_data_start,
sram_size, MT_MEMORY | MT_RW | MT_SECURE); sram_size, MT_MEMORY | MT_RW | MT_SECURE);
/* sram.incbin size */
sram_size = (char *)&__sram_incbin_end - (char *)&__sram_incbin_start;
mmap_add_region((unsigned long)&__sram_incbin_start,
(unsigned long)&__sram_incbin_start,
sram_size, MT_NON_CACHEABLE | MT_RW | MT_SECURE);
#else #else
/* TODO: Support other SoCs, Just support RK3399 now */ /* TODO: Support other SoCs, Just support RK3399 now */
return; return;
......
plat/rockchip/rk3399/drivers/dram/dcf_code.inc deleted 100644 → 0
View file @ 86a3b266
0x0 ,
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0xffffffff ,
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0xffffffff ,
0x4f77e204 ,
0xffffffff ,
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0xffffffff ,
0x4f77e20c ,
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0xe0000000 ,
plat/rockchip/rk3399/drivers/dram/dfs.c
View file @ d6845d3d
This diff is collapsed.
plat/rockchip/rk3399/drivers/dram/dfs.h
View file @ d6845d3d
...@@ -48,65 +48,25 @@ struct rk3399_sdram_default_config { ...@@ -48,65 +48,25 @@ struct rk3399_sdram_default_config {
unsigned char zqcsi; unsigned char zqcsi;
}; };
struct ddr_dts_config_timing {
unsigned int ddr3_speed_bin;
unsigned int pd_idle;
unsigned int sr_idle;
unsigned int sr_mc_gate_idle;
unsigned int srpd_lite_idle;
unsigned int standby_idle;
unsigned int auto_pd_dis_freq;
unsigned int ddr3_dll_dis_freq;
unsigned int phy_dll_dis_freq;
unsigned int ddr3_odt_dis_freq;
unsigned int ddr3_drv;
unsigned int ddr3_odt;
unsigned int phy_ddr3_ca_drv;
unsigned int phy_ddr3_dq_drv;
unsigned int phy_ddr3_odt;
unsigned int lpddr3_odt_dis_freq;
unsigned int lpddr3_drv;
unsigned int lpddr3_odt;
unsigned int phy_lpddr3_ca_drv;
unsigned int phy_lpddr3_dq_drv;
unsigned int phy_lpddr3_odt;
unsigned int lpddr4_odt_dis_freq;
unsigned int lpddr4_drv;
unsigned int lpddr4_dq_odt;
unsigned int lpddr4_ca_odt;
unsigned int phy_lpddr4_ca_drv;
unsigned int phy_lpddr4_ck_cs_drv;
unsigned int phy_lpddr4_dq_drv;
unsigned int phy_lpddr4_odt;
uint32_t available;
};
struct drv_odt_lp_config { struct drv_odt_lp_config {
uint32_t ddr3_speed_bin;
uint32_t pd_idle; uint32_t pd_idle;
uint32_t sr_idle; uint32_t sr_idle;
uint32_t sr_mc_gate_idle; uint32_t sr_mc_gate_idle;
uint32_t srpd_lite_idle; uint32_t srpd_lite_idle;
uint32_t standby_idle; uint32_t standby_idle;
uint32_t odt_en;
uint32_t ddr3_dll_dis_freq;/* for ddr3 only */
uint32_t phy_dll_dis_freq;
uint32_t odt_dis_freq;
uint32_t dram_side_drv; uint32_t dram_side_drv;
uint32_t dram_side_dq_odt; uint32_t dram_side_dq_odt;
uint32_t dram_side_ca_odt; uint32_t dram_side_ca_odt;
uint32_t phy_side_ca_drv;
uint32_t phy_side_ck_cs_drv;
uint32_t phy_side_dq_drv;
uint32_t phy_side_odt;
}; };
void ddr_dfs_init(void);
uint32_t ddr_set_rate(uint32_t hz); uint32_t ddr_set_rate(uint32_t hz);
uint32_t ddr_round_rate(uint32_t hz); uint32_t ddr_round_rate(uint32_t hz);
uint32_t ddr_get_rate(void); uint32_t ddr_get_rate(void);
void clr_dcf_irq(void); uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2);
uint32_t dts_timing_receive(uint32_t timing, uint32_t index); void dram_dfs_init(void);
void ddr_prepare_for_sys_suspend(void);
void ddr_prepare_for_sys_resume(void);
#endif #endif
plat/rockchip/rk3399/drivers/dram/dram.c
View file @ d6845d3d
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include <dram.h> #include <dram.h>
#include <plat_private.h> #include <plat_private.h>
#include <secure.h>
#include <soc.h> #include <soc.h>
#include <rk3399_def.h> #include <rk3399_def.h>
......
plat/rockchip/rk3399/drivers/dram/dram.h
View file @ d6845d3d
...@@ -30,111 +30,11 @@ ...@@ -30,111 +30,11 @@
#ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__ #ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__
#define __SOC_ROCKCHIP_RK3399_DRAM_H__ #define __SOC_ROCKCHIP_RK3399_DRAM_H__
#include <dram_regs.h>
#include <plat_private.h> #include <plat_private.h>
#include <stdint.h> #include <stdint.h>
#define CTL_BASE(ch) (0xffa80000 + (ch) * 0x8000)
#define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4)
#define PI_OFFSET 0x800
#define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET)
#define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4)
#define PHY_OFFSET 0x2000
#define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET)
#define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4)
#define MSCH_BASE(ch) (0xffa84000 + (ch) * 0x8000)
#define MSCH_ID_COREID 0x0
#define MSCH_ID_REVISIONID 0x4
#define MSCH_DEVICECONF 0x8
#define MSCH_DEVICESIZE 0xc
#define MSCH_DDRTIMINGA0 0x10
#define MSCH_DDRTIMINGB0 0x14
#define MSCH_DDRTIMINGC0 0x18
#define MSCH_DEVTODEV0 0x1c
#define MSCH_DDRMODE 0x110
#define MSCH_AGINGX0 0x1000
#define CIC_CTRL0 0x0
#define CIC_CTRL1 0x4
#define CIC_IDLE_TH 0x8
#define CIC_CG_WAIT_TH 0xc
#define CIC_STATUS0 0x10
#define CIC_STATUS1 0x14
#define CIC_CTRL2 0x18
#define CIC_CTRL3 0x1c
#define CIC_CTRL4 0x20
/* DENALI_CTL_00 */
#define START 1
/* DENALI_CTL_68 */
#define PWRUP_SREFRESH_EXIT (1 << 16)
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
#define PHY_DRV_ODT_Hi_Z 0x0
#define PHY_DRV_ODT_240 0x1
#define PHY_DRV_ODT_120 0x8
#define PHY_DRV_ODT_80 0x9
#define PHY_DRV_ODT_60 0xc
#define PHY_DRV_ODT_48 0xd
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
/*
* sys_reg bitfield struct
* [31] row_3_4_ch1
* [30] row_3_4_ch0
* [29:28] chinfo
* [27] rank_ch1
* [26:25] col_ch1
* [24] bk_ch1
* [23:22] cs0_row_ch1
* [21:20] cs1_row_ch1
* [19:18] bw_ch1
* [17:16] dbw_ch1;
* [15:13] ddrtype
* [12] channelnum
* [11] rank_ch0
* [10:9] col_ch0
* [8] bk_ch0
* [7:6] cs0_row_ch0
* [5:4] cs1_row_ch0
* [3:2] bw_ch0
* [1:0] dbw_ch0
*/
#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1)
#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
#define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1)
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7)
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1))
#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16))
#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1))
#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16))
#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16))
#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1))
#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + (ch) * 16))
#define SYS_REG_DEC_CS0_ROW(n, ch) (13 + (((n) >> (6 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + (ch) * 16))
#define SYS_REG_DEC_CS1_ROW(n, ch) (13 + (((n) >> (4 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16))
#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + (ch) * 16))
#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + (ch) * 16)) & 0x3))
#define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \
(0x1f<<(10+16))|((n)<<10))
#define CTL_REG_NUM 332
#define PHY_REG_NUM 959
#define PI_REG_NUM 200
enum { enum {
DDR3 = 3, DDR3 = 3,
LPDDR2 = 5, LPDDR2 = 5,
...@@ -259,6 +159,7 @@ struct rk3399_sdram_params { ...@@ -259,6 +159,7 @@ struct rk3399_sdram_params {
struct rk3399_ddr_pctl_regs pctl_regs; struct rk3399_ddr_pctl_regs pctl_regs;
struct rk3399_ddr_pi_regs pi_regs; struct rk3399_ddr_pi_regs pi_regs;
struct rk3399_ddr_publ_regs phy_regs; struct rk3399_ddr_publ_regs phy_regs;
uint32_t rx_cal_dqs[2][4];
}; };
extern __sramdata struct rk3399_sdram_params sdram_config; extern __sramdata struct rk3399_sdram_params sdram_config;
......
plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
View file @ d6845d3d
...@@ -267,21 +267,24 @@ static void ddr3_get_parameter(struct timing_related_config *timing_config, ...@@ -267,21 +267,24 @@ static void ddr3_get_parameter(struct timing_related_config *timing_config,
break; break;
} }
switch (timing_config->dramodt) { if (timing_config->odt)
case 60: switch (timing_config->dramodt) {
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60; case 60:
break; pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60;
case 40: break;
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40; case 40:
break; pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40;
case 120: break;
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120; case 120:
break; pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120;
case 0: break;
default: case 0:
default:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS;
break;
}
else
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS;
break;
}
pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl);
pdram_timing->mr[3] = 0; pdram_timing->mr[3] = 0;
...@@ -664,6 +667,9 @@ static void lpddr2_get_parameter(struct timing_related_config *timing_config, ...@@ -664,6 +667,9 @@ static void lpddr2_get_parameter(struct timing_related_config *timing_config,
#define LPDDR3_TADR (20) /* ns */ #define LPDDR3_TADR (20) /* ns */
#define LPDDR3_TMRZ (3) /* ns */ #define LPDDR3_TMRZ (3) /* ns */
/* FSP */
#define LPDDR3_TFC_LONG (250) /* ns */
/* /*
* Description: depend on input parameter "timing_config", * Description: depend on input parameter "timing_config",
* and calculate all lpddr3 * and calculate all lpddr3
...@@ -751,18 +757,21 @@ static void lpddr3_get_parameter(struct timing_related_config *timing_config, ...@@ -751,18 +757,21 @@ static void lpddr3_get_parameter(struct timing_related_config *timing_config,
break; break;
} }
pdram_timing->mr[0] = 0; pdram_timing->mr[0] = 0;
switch (timing_config->dramodt) { if (timing_config->odt)
case 60: switch (timing_config->dramodt) {
pdram_timing->mr11 = LPDDR3_ODT_60; case 60:
break; pdram_timing->mr11 = LPDDR3_ODT_60;
case 120: break;
pdram_timing->mr11 = LPDDR3_ODT_120; case 120:
break; pdram_timing->mr11 = LPDDR3_ODT_120;
case 240: break;
default: case 240:
pdram_timing->mr11 = LPDDR3_ODT_240; default:
break; pdram_timing->mr11 = LPDDR3_ODT_240;
} break;
}
else
pdram_timing->mr11 = LPDDR3_ODT_DIS;
pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000; pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000;
pdram_timing->tinit2 = LPDDR3_TINIT2; pdram_timing->tinit2 = LPDDR3_TINIT2;
...@@ -874,6 +883,9 @@ static void lpddr3_get_parameter(struct timing_related_config *timing_config, ...@@ -874,6 +883,9 @@ static void lpddr3_get_parameter(struct timing_related_config *timing_config,
pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000; pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000;
pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000; pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000;
pdram_timing->tcacd = pdram_timing->tadr + 2; pdram_timing->tcacd = pdram_timing->tadr + 2;
/* FSP */
pdram_timing->tfc_long = (LPDDR3_TFC_LONG * nmhz + 999) / 1000;
} }
#define LPDDR4_TINIT1 (200000) /* 200us */ #define LPDDR4_TINIT1 (200000) /* 200us */
...@@ -1113,47 +1125,52 @@ static void lpddr4_get_parameter(struct timing_related_config *timing_config, ...@@ -1113,47 +1125,52 @@ static void lpddr4_get_parameter(struct timing_related_config *timing_config,
break; break;
} }
pdram_timing->mr[0] = 0; pdram_timing->mr[0] = 0;
switch (timing_config->dramodt) { if (timing_config->odt) {
case 240: switch (timing_config->dramodt) {
tmp = LPDDR4_DQODT_240; case 240:
break; tmp = LPDDR4_DQODT_240;
case 120: break;
tmp = LPDDR4_DQODT_120; case 120:
break; tmp = LPDDR4_DQODT_120;
case 80: break;
tmp = LPDDR4_DQODT_80; case 80:
break; tmp = LPDDR4_DQODT_80;
case 60: break;
tmp = LPDDR4_DQODT_60; case 60:
break; tmp = LPDDR4_DQODT_60;
case 48: break;
tmp = LPDDR4_DQODT_48; case 48:
break; tmp = LPDDR4_DQODT_48;
case 40: break;
default: case 40:
tmp = LPDDR4_DQODT_40; default:
break; tmp = LPDDR4_DQODT_40;
} break;
switch (timing_config->caodt) { }
case 240:
pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp; switch (timing_config->caodt) {
break; case 240:
case 120: pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp;
pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp; break;
break; case 120:
case 80: pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp;
pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp; break;
break; case 80:
case 60: pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp;
pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp; break;
break; case 60:
case 48: pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp;
pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp; break;
break; case 48:
case 40: pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp;
default: break;
pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp; case 40:
break; default:
pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp;
break;
}
} else {
pdram_timing->mr11 = LPDDR4_CAODT_DIS | tmp;
} }
pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000; pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000;
......
plat/rockchip/rk3399/drivers/dram/suspend.c
View file @ d6845d3d
...@@ -34,6 +34,7 @@ ...@@ -34,6 +34,7 @@
#include <dram.h> #include <dram.h>
#include <pmu_regs.h> #include <pmu_regs.h>
#include <rk3399_def.h> #include <rk3399_def.h>
#include <secure.h>
#include <soc.h> #include <soc.h>
#include <suspend.h> #include <suspend.h>
...@@ -571,14 +572,15 @@ static __sramfunc void pctl_cfg(uint32_t ch, ...@@ -571,14 +572,15 @@ static __sramfunc void pctl_cfg(uint32_t ch,
sram_regcpy(PHY_REG(ch, 768), (uintptr_t)&params_phy[768], 38); sram_regcpy(PHY_REG(ch, 768), (uintptr_t)&params_phy[768], 38);
} }
static __sramfunc int dram_switch_to_phy_index1( static __sramfunc int dram_switch_to_next_index(
struct rk3399_sdram_params *sdram_params) struct rk3399_sdram_params *sdram_params)
{ {
uint32_t ch, ch_count; uint32_t ch, ch_count;
uint32_t fn = ((mmio_read_32(CTL_REG(0, 111)) >> 16) + 1) & 0x1;
mmio_write_32(CIC_BASE + CIC_CTRL0, mmio_write_32(CIC_BASE + CIC_CTRL0,
(((0x3 << 4) | (1 << 2) | 1) << 16) | (((0x3 << 4) | (1 << 2) | 1) << 16) |
(1 << 4) | (1 << 2) | 1); (fn << 4) | (1 << 2) | 1);
while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2))) while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)))
; ;
...@@ -591,7 +593,7 @@ static __sramfunc int dram_switch_to_phy_index1( ...@@ -591,7 +593,7 @@ static __sramfunc int dram_switch_to_phy_index1(
/* LPDDR4 f2 cann't do training, all training will fail */ /* LPDDR4 f2 cann't do training, all training will fail */
for (ch = 0; ch < ch_count; ch++) { for (ch = 0; ch < ch_count; ch++) {
mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1, mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1,
1 << 8); fn << 8);
/* data_training failed */ /* data_training failed */
if (data_training(ch, sdram_params, PI_FULL_TRAINING)) if (data_training(ch, sdram_params, PI_FULL_TRAINING))
...@@ -609,6 +611,7 @@ static __sramfunc int pctl_start(uint32_t channel_mask, ...@@ -609,6 +611,7 @@ static __sramfunc int pctl_start(uint32_t channel_mask,
struct rk3399_sdram_params *sdram_params) struct rk3399_sdram_params *sdram_params)
{ {
uint32_t count; uint32_t count;
uint32_t byte;
mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT);
mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT);
...@@ -640,6 +643,12 @@ static __sramfunc int pctl_start(uint32_t channel_mask, ...@@ -640,6 +643,12 @@ static __sramfunc int pctl_start(uint32_t channel_mask,
} }
mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT);
/* Restore the PHY_RX_CAL_DQS value */
for (byte = 0; byte < 4; byte++)
mmio_clrsetbits_32(PHY_REG(0, 57 + 128 * byte),
0xfff << 16,
sdram_params->rx_cal_dqs[0][byte]);
} }
if (channel_mask & (1 << 1)) { if (channel_mask & (1 << 1)) {
count = 0; count = 0;
...@@ -653,6 +662,12 @@ static __sramfunc int pctl_start(uint32_t channel_mask, ...@@ -653,6 +662,12 @@ static __sramfunc int pctl_start(uint32_t channel_mask,
} }
mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT);
/* Restore the PHY_RX_CAL_DQS value */
for (byte = 0; byte < 4; byte++)
mmio_clrsetbits_32(PHY_REG(1, 57 + 128 * byte),
0xfff << 16,
sdram_params->rx_cal_dqs[1][byte]);
} }
return 0; return 0;
...@@ -665,7 +680,7 @@ void dmc_save(void) ...@@ -665,7 +680,7 @@ void dmc_save(void)
uint32_t *params_pi; uint32_t *params_pi;
uint32_t *params_phy; uint32_t *params_phy;
uint32_t refdiv, postdiv2, postdiv1, fbdiv; uint32_t refdiv, postdiv2, postdiv1, fbdiv;
uint32_t tmp; uint32_t tmp, ch, byte;
params_ctl = sdram_params->pctl_regs.denali_ctl; params_ctl = sdram_params->pctl_regs.denali_ctl;
params_pi = sdram_params->pi_regs.denali_pi; params_pi = sdram_params->pi_regs.denali_pi;
...@@ -705,6 +720,12 @@ void dmc_save(void) ...@@ -705,6 +720,12 @@ void dmc_save(void)
sram_regcpy((uintptr_t)&params_phy[768], PHY_REG(0, 768), 38); sram_regcpy((uintptr_t)&params_phy[768], PHY_REG(0, 768), 38);
sram_regcpy((uintptr_t)&params_phy[896], PHY_REG(0, 896), 63); sram_regcpy((uintptr_t)&params_phy[896], PHY_REG(0, 896), 63);
for (ch = 0; ch < sdram_params->num_channels; ch++) {
for (byte = 0; byte < 4; byte++)
sdram_params->rx_cal_dqs[ch][byte] = (0xfff << 16) &
mmio_read_32(PHY_REG(ch, 57 + byte * 128));
}
/* set DENALI_PHY_957_DATA.PHY_DLL_RST_EN = 0x1 */ /* set DENALI_PHY_957_DATA.PHY_DLL_RST_EN = 0x1 */
params_phy[957] &= ~(0x3 << 24); params_phy[957] &= ~(0x3 << 24);
params_phy[957] |= 1 << 24; params_phy[957] |= 1 << 24;
...@@ -754,5 +775,5 @@ retry: ...@@ -754,5 +775,5 @@ retry:
dram_all_config(sdram_params); dram_all_config(sdram_params);
/* Switch to index 1 and prepare for DDR frequency switch. */ /* Switch to index 1 and prepare for DDR frequency switch. */
dram_switch_to_phy_index1(sdram_params); dram_switch_to_next_index(sdram_params);
} }
plat/rockchip/rk3399/drivers/m0/Makefile
View file @ d6845d3d
...@@ -46,32 +46,29 @@ export Q ...@@ -46,32 +46,29 @@ export Q
.SUFFIXES: .SUFFIXES:
INCLUDES += -Iinclude/ INCLUDES += -Iinclude/ \
-I../../include/shared/
# NOTE: Add C source files here # NOTE: Add C source files here
C_SOURCES := src/startup.c \ C_SOURCES := src/startup.c \
src/main.c src/main.c \
src/suspend.c \
src/dram.c \
src/stopwatch.c
# Flags definition # Flags definition
CFLAGS := -g COMMON_FLAGS := -g -mcpu=$(ARCH) -mthumb -Wall -O3 -nostdlib -mfloat-abi=soft
ASFLAGS := -g -Wa,--gdwarf-2 CFLAGS := -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-common
ASFLAGS := -Wa,--gdwarf-2
ASFLAGS += -mcpu=$(ARCH) -mthumb -Wall -ffunction-sections -O3 LDFLAGS := -Wl,--gc-sections -Wl,--build-id=none
CFLAGS += -mcpu=$(ARCH) -mthumb -Wall -ffunction-sections -O3
LDFLAGS := -mcpu=$(ARCH) -mthumb -g -nostartfiles -nostdlib -O3
LDFLAGS += -Wl,--gc-sections -Wl,--build-id=none
# Cross tool # Cross tool
CC := ${M0_CROSS_COMPILE}gcc CC := ${M0_CROSS_COMPILE}gcc
CPP := ${M0_CROSS_COMPILE}cpp CPP := ${M0_CROSS_COMPILE}cpp
AS := ${M0_CROSS_COMPILE}gcc
AR := ${M0_CROSS_COMPILE}ar AR := ${M0_CROSS_COMPILE}ar
LD := ${M0_CROSS_COMPILE}ld
OC := ${M0_CROSS_COMPILE}objcopy OC := ${M0_CROSS_COMPILE}objcopy
OD := ${M0_CROSS_COMPILE}objdump OD := ${M0_CROSS_COMPILE}objdump
NM := ${M0_CROSS_COMPILE}nm NM := ${M0_CROSS_COMPILE}nm
PP := ${M0_CROSS_COMPILE}gcc -E ${CFLAGS}
# NOTE: The line continuation '\' is required in the next define otherwise we # NOTE: The line continuation '\' is required in the next define otherwise we
# end up with a line-feed characer at the end of the last c filename. # end up with a line-feed characer at the end of the last c filename.
...@@ -83,10 +80,11 @@ endef ...@@ -83,10 +80,11 @@ endef
SOURCES := $(C_SOURCES) SOURCES := $(C_SOURCES)
OBJS := $(addprefix $(BUILD)/,$(call SOURCES_TO_OBJS,$(SOURCES))) OBJS := $(addprefix $(BUILD)/,$(call SOURCES_TO_OBJS,$(SOURCES)))
LINKERFILE := src/rk3399m0.ld LINKERFILE := $(BUILD)/$(PLAT_M0).ld
MAPFILE := $(BUILD)/$(PLAT_M0).map MAPFILE := $(BUILD)/$(PLAT_M0).map
ELF := $(BUILD)/$(PLAT_M0).elf ELF := $(BUILD)/$(PLAT_M0).elf
BIN := $(BUILD)/$(PLAT_M0).bin BIN := $(BUILD)/$(PLAT_M0).bin
LINKERFILE_SRC := src/$(PLAT_M0).ld.S
# Function definition related compilation # Function definition related compilation
define MAKE_C define MAKE_C
...@@ -95,7 +93,7 @@ $(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2)))) ...@@ -95,7 +93,7 @@ $(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
$(OBJ) : $(2) $(OBJ) : $(2)
@echo " CC $$<" @echo " CC $$<"
$$(Q)$$(CC) $$(CFLAGS) $$(INCLUDES) -MMD -MT $$@ -c $$< -o $$@ $$(Q)$$(CC) $$(COMMON_FLAGS) $$(CFLAGS) $$(INCLUDES) -MMD -MT $$@ -c $$< -o $$@
endef endef
define MAKE_S define MAKE_S
...@@ -103,7 +101,7 @@ $(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2)))) ...@@ -103,7 +101,7 @@ $(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
$(OBJ) : $(2) $(OBJ) : $(2)
@echo " AS $$<" @echo " AS $$<"
$$(Q)$$(AS) $$(ASFLAGS) -c $$< -o $$@ $$(Q)$$(CC) -x assembler-with-cpp $$(COMMON_FLAGS) $$(ASFLAGS) -c $$< -o $$@
endef endef
define MAKE_OBJS define MAKE_OBJS
...@@ -118,13 +116,15 @@ define MAKE_OBJS ...@@ -118,13 +116,15 @@ define MAKE_OBJS
$(and $(REMAIN),$(error Unexpected source files present: $(REMAIN))) $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN)))
endef endef
.PHONY: all .DEFAULT_GOAL := $(BIN)
all: $(BIN)
$(LINKERFILE): $(LINKERFILE_SRC)
$(CC) $(COMMON_FLAGS) $(INCLUDES) -P -E -D__LINKER__ -MMD -MF $@.d -MT $@ -o $@ $<
-include $(LINKERFILE).d
$(ELF) : $(OBJS) $(LINKERFILE) $(ELF) : $(OBJS) $(LINKERFILE)
@echo " LD $@" @echo " LD $@"
$(Q)$(CC) -o $@ $(LDFLAGS) -Wl,-Map=$(MAPFILE) -Wl,-T$(LINKERFILE) \ $(Q)$(CC) -o $@ $(COMMON_FLAGS) $(LDFLAGS) -Wl,-Map=$(MAPFILE) -Wl,-T$(LINKERFILE) $(OBJS)
$(OBJS)
$(BIN) : $(ELF) $(BIN) : $(ELF)
@echo " BIN $@" @echo " BIN $@"
......
plat/rockchip/rk3399/drivers/pmu/rk3399m0.h → plat/rockchip/rk3399/drivers/m0/include/addressmap.h
View file @ d6845d3d
...@@ -28,13 +28,12 @@ ...@@ -28,13 +28,12 @@
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
*/ */
#ifndef __RK3399M0_H__ #ifndef __ROCKCHIP_RK3399_M0_INCLUDE_SHARED_ADDRESSMAP_H__
#define __RK3399M0_H__ #define __ROCKCHIP_RK3399_M0_INCLUDE_SHARED_ADDRESSMAP_H__
/* pmu_fw.c */ #include <addressmap_shared.h>
extern char rk3399m0_bin[];
extern char rk3399m0_bin_end[];
#define M0_BINCODE_BASE ((uintptr_t)rk3399m0_bin) /* Registers base address for M0 */
#define MMIO_BASE 0x40000000
#endif /* __RK3399M0_H__ */ #endif /* __ROCKCHIP_RK3399_M0_INCLUDE_SHARED_ADDRESSMAP_H__ */
plat/rockchip/rk3399/drivers/m0/include/rk3399_mcu.h
View file @ d6845d3d
...@@ -31,11 +31,28 @@ ...@@ -31,11 +31,28 @@
#ifndef __RK3399_MCU_H__ #ifndef __RK3399_MCU_H__
#define __RK3399_MCU_H__ #define __RK3399_MCU_H__
#define readl(c) ({unsigned int __v = \ #include <addressmap.h>
typedef unsigned int uint32_t;
#define mmio_read_32(c) ({unsigned int __v = \
(*(volatile unsigned int *)(c)); __v; }) (*(volatile unsigned int *)(c)); __v; })
#define writel(v, c) ((*(volatile unsigned int *) (c)) = (v)) #define mmio_write_32(c, v) ((*(volatile unsigned int *)(c)) = (v))
#define mmio_clrbits_32(addr, clear) \
mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)))
#define mmio_setbits_32(addr, set) \
mmio_write_32(addr, (mmio_read_32(addr)) | (set))
#define mmio_clrsetbits_32(addr, clear, set) \
mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MCU_BASE 0x40000000 void handle_suspend(void);
#define PMU_BASE (MCU_BASE + 0x07310000) void handle_dram(void);
void stopwatch_init_usecs_expire(unsigned int usecs);
int stopwatch_expired(void);
void stopwatch_reset(void);
#endif /* __RK3399_MCU_H__ */ #endif /* __RK3399_MCU_H__ */
plat/rockchip/rk3399/drivers/m0/src/dram.c 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <dram_regs.h>
#include <m0_param.h>
#include <pmu_bits.h>
#include <pmu_regs.h>
#include "misc_regs.h"
#include "rk3399_mcu.h"
static uint32_t gatedis_con0;
static void idle_port(void)
{
gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0);
mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff);
mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
(1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1));
while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) &
((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) !=
((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0)))
continue;
}
static void deidle_port(void)
{
mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
(1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1));
while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) &
((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0)))
continue;
/* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0);
}
static void ddr_set_pll(void)
{
mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE));
mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1));
mmio_write_32(CRU_BASE + CRU_DPLL_CON0,
mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0));
mmio_write_32(CRU_BASE + CRU_DPLL_CON1,
mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1));
mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0));
while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0)
continue;
mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE));
}
void handle_dram(void)
{
mmio_setbits_32(PHY_REG(0, 927), (1 << 22));
mmio_setbits_32(PHY_REG(1, 927), (1 << 22));
idle_port();
mmio_write_32(CIC_BASE + CIC_CTRL0,
(((0x3 << 4) | (1 << 2) | 1) << 16) |
(1 << 2) | 1 |
mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT));
while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0)
continue;
ddr_set_pll();
mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002);
while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0)
continue;
deidle_port();
mmio_clrbits_32(PHY_REG(0, 927), (1 << 22));
mmio_clrbits_32(PHY_REG(1, 927), (1 << 22));
}
plat/rockchip/rk3399/drivers/m0/src/main.c
View file @ d6845d3d
...@@ -28,44 +28,24 @@ ...@@ -28,44 +28,24 @@
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
*/ */
#include <m0_param.h>
#include "rk3399_mcu.h" #include "rk3399_mcu.h"
#define PMU_PWRMODE_CON 0x20 __attribute__((noreturn)) void main(void)
#define PMU_POWER_ST 0x78
#define M0_SCR 0xe000ed10 /* System Control Register (SCR) */
#define SCR_SLEEPDEEP_SHIFT (1 << 2)
static void system_wakeup(void)
{ {
unsigned int status_value; switch (mmio_read_32(PARAM_ADDR + PARAM_M0_FUNC)) {
unsigned int mode_con; case M0_FUNC_SUSPEND:
handle_suspend();
while (1) { break;
status_value = readl(PMU_BASE + PMU_POWER_ST); case M0_FUNC_DRAM:
if (status_value) { handle_dram();
mode_con = readl(PMU_BASE + PMU_PWRMODE_CON); break;
writel(mode_con & (~0x01), default:
PMU_BASE + PMU_PWRMODE_CON); break;
return;
}
} }
}
int main(void) mmio_write_32(PARAM_ADDR + PARAM_M0_DONE, M0_DONE_FLAG);
{
unsigned int reg_src;
system_wakeup();
reg_src = readl(M0_SCR);
/* m0 enter deep sleep mode */
writel(reg_src | SCR_SLEEPDEEP_SHIFT, M0_SCR);
for (;;) for (;;)
__asm volatile("wfi"); __asm__ volatile ("wfi");
return 0;
} }
plat/rockchip/rk3399/drivers/m0/src/rk3399m0.ld → plat/rockchip/rk3399/drivers/m0/src/rk3399m0.ld.S
View file @ d6845d3d
...@@ -28,12 +28,16 @@ ...@@ -28,12 +28,16 @@
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
*/ */
#include <m0_param.h>
OUTPUT_FORMAT("elf32-littlearm") OUTPUT_FORMAT("elf32-littlearm")
SECTIONS { SECTIONS {
.m0_bin 0 : { .m0_bin 0 : {
KEEP(*(.isr_vector)) KEEP(*(.isr_vector))
ASSERT(. == 0xc0, "ISR vector has the wrong size."); ASSERT(. == 0xc0, "ISR vector has the wrong size.");
ASSERT(. == PARAM_ADDR, "M0 params should go right behind ISR table.");
. += PARAM_M0_SIZE;
*(.text*) *(.text*)
*(.rodata*) *(.rodata*)
*(.data*) *(.data*)
......
plat/rockchip/rk3399/drivers/m0/src/stopwatch.c 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <m0_param.h>
#include "rk3399_mcu.h"
/* use 24MHz SysTick */
#define US_TO_CYCLE(US) (US * 24)
#define SYST_CST 0xe000e010
/* enable counter */
#define ENABLE (1 << 0)
/* count down to 0 does not cause SysTick exception to pend */
#define TICKINT (1 << 1)
/* core clock used for SysTick */
#define CLKSOURCE (1 << 2)
#define COUNTFLAG (1 << 16)
#define SYST_RVR 0xe000e014
#define MAX_VALUE 0xffffff
#define MAX_USECS (MAX_VALUE / US_TO_CYCLE(1))
#define SYST_CVR 0xe000e018
#define SYST_CALIB 0xe000e01c
unsigned int remaining_usecs;
static inline void stopwatch_set_usecs(void)
{
unsigned int cycle;
unsigned int usecs = MIN(MAX_USECS, remaining_usecs);
remaining_usecs -= usecs;
cycle = US_TO_CYCLE(usecs);
mmio_write_32(SYST_RVR, cycle);
mmio_write_32(SYST_CVR, 0);
mmio_write_32(SYST_CST, ENABLE | TICKINT | CLKSOURCE);
}
void stopwatch_init_usecs_expire(unsigned int usecs)
{
/*
* Enter an inifite loop if the stopwatch is in use. This will allow the
* state to be analyzed with a debugger.
*/
if (mmio_read_32(SYST_CST) & ENABLE)
while (1)
;
remaining_usecs = usecs;
stopwatch_set_usecs();
}
int stopwatch_expired(void)
{
int val = mmio_read_32(SYST_CST);
if ((val & COUNTFLAG) || !(val & ENABLE)) {
if (!remaining_usecs)
return 1;
stopwatch_set_usecs();
}
return 0;
}
void stopwatch_reset(void)
{
mmio_clrbits_32(SYST_CST, ENABLE);
remaining_usecs = 0;
}
plat/rockchip/rk3399/drivers/m0/src/suspend.c 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <pmu_regs.h>
#include "rk3399_mcu.h"
#define M0_SCR 0xe000ed10 /* System Control Register (SCR) */
#define SCR_SLEEPDEEP_SHIFT (1 << 2)
void handle_suspend(void)
{
unsigned int status_value;
while (1) {
status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST);
if (status_value) {
mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01);
return;
}
}
/* m0 enter deep sleep mode */
mmio_setbits_32(M0_SCR, SCR_SLEEPDEEP_SHIFT);
}
plat/rockchip/rk3399/drivers/pmu/m0_ctl.c 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <assert.h>
#include <debug.h>
#include <delay_timer.h>
#include <mmio.h>
#include <m0_ctl.h>
#include <plat_private.h>
#include <rk3399_def.h>
#include <secure.h>
#include <soc.h>
void m0_init(void)
{
/* secure config for M0 */
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7));
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12));
/* set the execute address for M0 */
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3),
BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff,
0xffff, 0));
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7),
BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf,
0xf, 0));
/* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02);
/*
* To switch the parent to xin24M and div == 1,
*
* We need to close most of the PLLs and clocks except the OSC 24MHz
* durning suspend, and this should be enough to supplies the ddrfreq,
* For the simple handle, we just keep the fixed 24MHz to supply the
* suspend and ddrfreq directly.
*/
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0,
BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8));
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5));
}
void m0_start(void)
{
/* enable clocks for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
BITS_WITH_WMASK(0x0, 0xf, 0));
/* clean the PARAM_M0_DONE flag, mean that M0 will start working */
mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0);
dmbst();
mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
BITS_WITH_WMASK(0x0, 0x4, 0));
udelay(5);
/* start M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
BITS_WITH_WMASK(0x0, 0x20, 0));
dmbst();
}
void m0_stop(void)
{
/* stop M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
BITS_WITH_WMASK(0x24, 0x24, 0));
/* disable clocks for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
BITS_WITH_WMASK(0xf, 0xf, 0));
}
void m0_wait_done(void)
{
do {
/*
* Don't starve the M0 for access to SRAM, so delay before
* reading the PARAM_M0_DONE value again.
*/
udelay(5);
dsb();
} while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG);
/*
* Let the M0 settle into WFI before we leave. This is so we don't reset
* the M0 in a bad spot which can cause problems with the M0.
*/
udelay(10);
dsb();
}
plat/rockchip/rk3399/drivers/pmu/m0_ctl.h 0 → 100644
View file @ d6845d3d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __M0_CTL_H__
#define __M0_CTL_H__
#include <m0_param.h>
#define M0_BINCODE_BASE ((uintptr_t)rk3399m0_bin)
#define M0_PARAM_ADDR (M0_BINCODE_BASE + PARAM_ADDR)
/* pmu_fw.c */
extern char rk3399m0_bin[];
extern char rk3399m0_bin_end[];
extern void m0_init(void);
extern void m0_start(void);
extern void m0_stop(void);
extern void m0_wait_done(void);
#endif /* __M0_CTL_H__ */
plat/rockchip/rk3399/drivers/pmu/pmu.c
View file @ d6845d3d
...@@ -33,21 +33,23 @@ ...@@ -33,21 +33,23 @@
#include <bakery_lock.h> #include <bakery_lock.h>
#include <debug.h> #include <debug.h>
#include <delay_timer.h> #include <delay_timer.h>
#include <dfs.h>
#include <errno.h> #include <errno.h>
#include <gpio.h> #include <gpio.h>
#include <mmio.h> #include <mmio.h>
#include <m0_ctl.h>
#include <platform.h> #include <platform.h>
#include <platform_def.h> #include <platform_def.h>
#include <plat_params.h> #include <plat_params.h>
#include <plat_private.h> #include <plat_private.h>
#include <rk3399_def.h> #include <rk3399_def.h>
#include <pmu_sram.h> #include <pmu_sram.h>
#include <secure.h>
#include <soc.h> #include <soc.h>
#include <pmu.h> #include <pmu.h>
#include <pmu_com.h> #include <pmu_com.h>
#include <pwm.h> #include <pwm.h>
#include <bl31.h> #include <bl31.h>
#include <rk3399m0.h>
#include <suspend.h> #include <suspend.h>
DEFINE_BAKERY_LOCK(rockchip_pd_lock); DEFINE_BAKERY_LOCK(rockchip_pd_lock);
...@@ -1065,36 +1067,10 @@ static void resume_gpio(void) ...@@ -1065,36 +1067,10 @@ static void resume_gpio(void)
} }
} }
static void m0_clock_init(void) static void m0_configure_suspend(void)
{ {
/* enable clocks for M0 */ /* set PARAM to M0_FUNC_SUSPEND */
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_SUSPEND);
BITS_WITH_WMASK(0x0, 0x2f, 0));
/* switch the parent to xin24M and div == 1 */
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0,
BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8));
/* start M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
BITS_WITH_WMASK(0x0, 0x24, 0));
/* gating disable for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, BIT_WITH_WMSK(1));
}
static void m0_reset(void)
{
/* stop M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
BITS_WITH_WMASK(0x24, 0x24, 0));
/* recover gating bit for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, WMSK_BIT(1));
/* disable clocks for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
BITS_WITH_WMASK(0x2f, 0x2f, 0));
} }
static int sys_pwr_domain_suspend(void) static int sys_pwr_domain_suspend(void)
...@@ -1102,6 +1078,7 @@ static int sys_pwr_domain_suspend(void) ...@@ -1102,6 +1078,7 @@ static int sys_pwr_domain_suspend(void)
uint32_t wait_cnt = 0; uint32_t wait_cnt = 0;
uint32_t status = 0; uint32_t status = 0;
ddr_prepare_for_sys_suspend();
dmc_save(); dmc_save();
pmu_scu_b_pwrdn(); pmu_scu_b_pwrdn();
...@@ -1117,11 +1094,12 @@ static int sys_pwr_domain_suspend(void) ...@@ -1117,11 +1094,12 @@ static int sys_pwr_domain_suspend(void)
sys_slp_config(); sys_slp_config();
m0_clock_init(); m0_configure_suspend();
m0_start();
pmu_sgrf_rst_hld(); pmu_sgrf_rst_hld();
mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
(PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) |
CPU_BOOT_ADDR_WMASK); CPU_BOOT_ADDR_WMASK);
...@@ -1173,7 +1151,7 @@ static int sys_pwr_domain_resume(void) ...@@ -1173,7 +1151,7 @@ static int sys_pwr_domain_resume(void)
udelay(300); udelay(300);
enable_dvfs_plls(); enable_dvfs_plls();
secure_watchdog_restore(); secure_watchdog_enable();
/* restore clk_ddrc_bpll_src_en gate */ /* restore clk_ddrc_bpll_src_en gate */
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),
...@@ -1189,7 +1167,7 @@ static int sys_pwr_domain_resume(void) ...@@ -1189,7 +1167,7 @@ static int sys_pwr_domain_resume(void)
mmio_write_32(PMU_BASE + PMU_WAKEUP_STATUS, 0xffffffff); mmio_write_32(PMU_BASE + PMU_WAKEUP_STATUS, 0xffffffff);
mmio_write_32(PMU_BASE + PMU_WKUP_CFG4, 0x00); mmio_write_32(PMU_BASE + PMU_WKUP_CFG4, 0x00);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
(cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) |
CPU_BOOT_ADDR_WMASK); CPU_BOOT_ADDR_WMASK);
...@@ -1241,8 +1219,9 @@ static int sys_pwr_domain_resume(void) ...@@ -1241,8 +1219,9 @@ static int sys_pwr_domain_resume(void)
BIT(PMU_CLR_GIC)); BIT(PMU_CLR_GIC));
plat_rockchip_gic_cpuif_enable(); plat_rockchip_gic_cpuif_enable();
m0_stop();
m0_reset(); ddr_prepare_for_sys_resume();
return 0; return 0;
} }
...@@ -1328,7 +1307,7 @@ void plat_rockchip_pmu_init(void) ...@@ -1328,7 +1307,7 @@ void plat_rockchip_pmu_init(void)
psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff;
/* config cpu's warm boot address */ /* config cpu's warm boot address */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
(cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) |
CPU_BOOT_ADDR_WMASK); CPU_BOOT_ADDR_WMASK);
mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE); mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE);
......
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