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Commit d7b5f408 authored by Jimmy Brisson's avatar Jimmy Brisson Committed by laurenw-arm
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Increase type widths to satisfy width requirements 



Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:

    bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
    The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
    0x3c0U" (32 bits) is less that the right hand operand
    "18446744073709547519ULL" (64 bits).

This also resolves MISRA defects such as:

    bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
    In the expression "3U << 20", shifting more than 7 bits, the number
    of bits in the essential type of the left expression, "3U", is
    not allowed.

Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.

This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,

    92407e73        and     x19, x19, #0xffffffff

from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.

The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.

Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16
Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
parent 7ad39818
Hide whitespace changes
Inline Side-by-side
bl1/aarch64/bl1_context_mgmt.c
View file @ d7b5f408
......@@ -78,8 +78,8 @@ void bl1_prepare_next_image(unsigned int image_id)
mode = MODE_EL2;
}
next_bl_ep->spsr = (uint32_t)SPSR_64(mode, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
next_bl_ep->spsr = (uint32_t)SPSR_64((uint64_t) mode,
(uint64_t)MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
/* Allow platform to make change */
bl1_plat_set_ep_info(image_id, next_bl_ep);
......
bl31/bl31.ld.S
View file @ d7b5f408
......@@ -37,7 +37,7 @@ SECTIONS
.text . : {
__TEXT_START__ = .;
*bl31_entrypoint.o(.text*)
*(SORT_BY_ALIGNMENT(.text*))
*(SORT_BY_ALIGNMENT(SORT(.text*)))
*(.vectors)
. = ALIGN(PAGE_SIZE);
__TEXT_END__ = .;
......
bl32/tsp/aarch64/tsp_entrypoint.S
View file @ d7b5f408
......@@ -60,7 +60,7 @@ func tsp_entrypoint _align=3
*/
pie_fixup:
ldr x0, =pie_fixup
and x0, x0, #~(PAGE_SIZE - 1)
and x0, x0, #~(PAGE_SIZE_MASK)
mov_imm x1, (BL32_LIMIT - BL32_BASE)
add x1, x1, x0
bl fixup_gdt_reloc
......
common/bl_common.c
View file @ d7b5f408
......@@ -50,8 +50,8 @@ static int dyn_is_auth_disabled(void)
uintptr_t page_align(uintptr_t value, unsigned dir)
{
/* Round up the limit to the next page boundary */
if ((value & (PAGE_SIZE - 1U)) != 0U) {
value &= ~(PAGE_SIZE - 1U);
if ((value & PAGE_SIZE_MASK) != 0U) {
value &= ~PAGE_SIZE_MASK;
if (dir == UP)
value += PAGE_SIZE;
}
......
drivers/arm/cci/cci.c
View file @ d7b5f408
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -52,11 +52,11 @@ static bool validate_cci_map(const int *map)
return false;
}
if ((valid_cci_map & (1U << slave_if_id)) != 0U) {
if ((valid_cci_map & (1UL << slave_if_id)) != 0U) {
ERROR("Multiple masters are assigned same slave interface ID\n");
return false;
}
valid_cci_map |= 1U << slave_if_id;
valid_cci_map |= 1UL << slave_if_id;
}
if (valid_cci_map == 0U) {
......
drivers/arm/tzc/tzc400.c
View file @ d7b5f408
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -91,9 +91,9 @@ static void _tzc400_set_gate_keeper(uintptr_t base,
open_status = get_gate_keeper_os(base);
if (val != 0)
open_status |= (1U << filter);
open_status |= (1UL << filter);
else
open_status &= ~(1U << filter);
open_status &= ~(1UL << filter);
_tzc400_write_gate_keeper(base, (open_status & GATE_KEEPER_OR_MASK) <<
GATE_KEEPER_OR_SHIFT);
......
drivers/arm/tzc/tzc_common_private.h
View file @ d7b5f408
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -30,13 +30,13 @@
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
region_no) + \
(u_register_t)region_no) + \
TZC_##macro_name##_REGION_BASE_LOW_0_OFFSET, \
(uint32_t)region_base); \
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
region_no) + \
(u_register_t)region_no) + \
TZC_##macro_name##_REGION_BASE_HIGH_0_OFFSET, \
(uint32_t)(region_base >> 32)); \
}
......@@ -48,15 +48,15 @@
unsigned long long region_top) \
{ \
mmio_write_32(base + \
TZC_REGION_OFFSET \
(TZC_##macro_name##_REGION_SIZE, \
region_no) + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
(u_register_t)region_no) + \
TZC_##macro_name##_REGION_TOP_LOW_0_OFFSET, \
(uint32_t)region_top); \
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
region_no) + \
(u_register_t)region_no) + \
TZC_##macro_name##_REGION_TOP_HIGH_0_OFFSET, \
(uint32_t)(region_top >> 32)); \
}
......@@ -70,7 +70,7 @@
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
region_no) + \
(u_register_t)region_no) + \
TZC_##macro_name##_REGION_ATTR_0_OFFSET, \
attr); \
}
......@@ -84,7 +84,7 @@
mmio_write_32(base + \
TZC_REGION_OFFSET( \
TZC_##macro_name##_REGION_SIZE, \
region_no) + \
(u_register_t)region_no) + \
TZC_##macro_name##_REGION_ID_ACCESS_0_OFFSET, \
val); \
}
......
include/arch/aarch32/arch.h
View file @ d7b5f408
......@@ -183,23 +183,23 @@
/* CPACR definitions */
#define CPACR_FPEN(x) ((x) << 20)
#define CPACR_FP_TRAP_PL0 U(0x1)
#define CPACR_FP_TRAP_ALL U(0x2)
#define CPACR_FP_TRAP_NONE U(0x3)
#define CPACR_FP_TRAP_PL0 UL(0x1)
#define CPACR_FP_TRAP_ALL UL(0x2)
#define CPACR_FP_TRAP_NONE UL(0x3)
/* SCR definitions */
#define SCR_TWE_BIT (U(1) << 13)
#define SCR_TWI_BIT (U(1) << 12)
#define SCR_SIF_BIT (U(1) << 9)
#define SCR_HCE_BIT (U(1) << 8)
#define SCR_SCD_BIT (U(1) << 7)
#define SCR_NET_BIT (U(1) << 6)
#define SCR_AW_BIT (U(1) << 5)
#define SCR_FW_BIT (U(1) << 4)
#define SCR_EA_BIT (U(1) << 3)
#define SCR_FIQ_BIT (U(1) << 2)
#define SCR_IRQ_BIT (U(1) << 1)
#define SCR_NS_BIT (U(1) << 0)
#define SCR_TWE_BIT (UL(1) << 13)
#define SCR_TWI_BIT (UL(1) << 12)
#define SCR_SIF_BIT (UL(1) << 9)
#define SCR_HCE_BIT (UL(1) << 8)
#define SCR_SCD_BIT (UL(1) << 7)
#define SCR_NET_BIT (UL(1) << 6)
#define SCR_AW_BIT (UL(1) << 5)
#define SCR_FW_BIT (UL(1) << 4)
#define SCR_EA_BIT (UL(1) << 3)
#define SCR_FIQ_BIT (UL(1) << 2)
#define SCR_IRQ_BIT (UL(1) << 1)
#define SCR_NS_BIT (UL(1) << 0)
#define SCR_VALID_BIT_MASK U(0x33ff)
#define SCR_RESET_VAL U(0x0)
......
include/arch/aarch64/arch.h
View file @ d7b5f408
......@@ -326,34 +326,34 @@
/* CPACR_El1 definitions */
#define CPACR_EL1_FPEN(x) ((x) << 20)
#define CPACR_EL1_FP_TRAP_EL0 U(0x1)
#define CPACR_EL1_FP_TRAP_ALL U(0x2)
#define CPACR_EL1_FP_TRAP_NONE U(0x3)
#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
#define CPACR_EL1_FP_TRAP_ALL UL(0x2)
#define CPACR_EL1_FP_TRAP_NONE UL(0x3)
/* SCR definitions */
#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
#define SCR_TWEDEL_SHIFT U(30)
#define SCR_TWEDEL_MASK ULL(0xf)
#define SCR_TWEDEn_BIT (UL(1) << 29)
#define SCR_ECVEN_BIT (U(1) << 28)
#define SCR_FGTEN_BIT (U(1) << 27)
#define SCR_ATA_BIT (U(1) << 26)
#define SCR_FIEN_BIT (U(1) << 21)
#define SCR_EEL2_BIT (U(1) << 18)
#define SCR_API_BIT (U(1) << 17)
#define SCR_APK_BIT (U(1) << 16)
#define SCR_TERR_BIT (U(1) << 15)
#define SCR_TWE_BIT (U(1) << 13)
#define SCR_TWI_BIT (U(1) << 12)
#define SCR_ST_BIT (U(1) << 11)
#define SCR_RW_BIT (U(1) << 10)
#define SCR_SIF_BIT (U(1) << 9)
#define SCR_HCE_BIT (U(1) << 8)
#define SCR_SMD_BIT (U(1) << 7)
#define SCR_EA_BIT (U(1) << 3)
#define SCR_FIQ_BIT (U(1) << 2)
#define SCR_IRQ_BIT (U(1) << 1)
#define SCR_NS_BIT (U(1) << 0)
#define SCR_ECVEN_BIT (UL(1) << 28)
#define SCR_FGTEN_BIT (UL(1) << 27)
#define SCR_ATA_BIT (UL(1) << 26)
#define SCR_FIEN_BIT (UL(1) << 21)
#define SCR_EEL2_BIT (UL(1) << 18)
#define SCR_API_BIT (UL(1) << 17)
#define SCR_APK_BIT (UL(1) << 16)
#define SCR_TERR_BIT (UL(1) << 15)
#define SCR_TWE_BIT (UL(1) << 13)
#define SCR_TWI_BIT (UL(1) << 12)
#define SCR_ST_BIT (UL(1) << 11)
#define SCR_RW_BIT (UL(1) << 10)
#define SCR_SIF_BIT (UL(1) << 9)
#define SCR_HCE_BIT (UL(1) << 8)
#define SCR_SMD_BIT (UL(1) << 7)
#define SCR_EA_BIT (UL(1) << 3)
#define SCR_FIQ_BIT (UL(1) << 2)
#define SCR_IRQ_BIT (UL(1) << 1)
#define SCR_NS_BIT (UL(1) << 0)
#define SCR_VALID_BIT_MASK U(0x2f8f)
#define SCR_RESET_VAL SCR_RES1_BITS
......
include/arch/aarch64/el3_common_macros.S
View file @ d7b5f408
......@@ -305,7 +305,7 @@
*/
pie_fixup:
ldr x0, =pie_fixup
and x0, x0, #~(PAGE_SIZE - 1)
and x0, x0, #~(PAGE_SIZE_MASK)
mov_imm x1, \_pie_fixup_size
add x1, x1, x0
bl fixup_gdt_reloc
......
include/export/common/ep_info_exp.h
View file @ d7b5f408
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -25,10 +25,10 @@
#endif
/* Security state of the image. */
#define EP_SECURITY_MASK U(0x1)
#define EP_SECURITY_SHIFT U(0)
#define EP_SECURE U(0x0)
#define EP_NON_SECURE U(0x1)
#define EP_SECURITY_MASK UL(0x1)
#define EP_SECURITY_SHIFT UL(0)
#define EP_SECURE UL(0x0)
#define EP_NON_SECURE UL(0x1)
/* Endianness of the image. */
#define EP_EE_MASK U(0x2)
......
include/lib/pmf/pmf.h
View file @ d7b5f408
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -14,13 +14,13 @@
/*
* Constants used for/by PMF services.
*/
#define PMF_ARM_TIF_IMPL_ID U(0x41)
#define PMF_ARM_TIF_IMPL_ID UL(0x41)
#define PMF_TID_SHIFT 0
#define PMF_TID_MASK (U(0xFF) << PMF_TID_SHIFT)
#define PMF_TID_MASK (UL(0xFF) << PMF_TID_SHIFT)
#define PMF_SVC_ID_SHIFT 10
#define PMF_SVC_ID_MASK (U(0x3F) << PMF_SVC_ID_SHIFT)
#define PMF_SVC_ID_MASK (UL(0x3F) << PMF_SVC_ID_SHIFT)
#define PMF_IMPL_ID_SHIFT 24
#define PMF_IMPL_ID_MASK (U(0xFF) << PMF_IMPL_ID_SHIFT)
#define PMF_IMPL_ID_MASK (UL(0xFF) << PMF_IMPL_ID_SHIFT)
/*
* Flags passed to PMF_REGISTER_SERVICE
......
include/lib/pmf/pmf_helpers.h
View file @ d7b5f408
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -174,24 +174,26 @@ typedef struct pmf_svc_desc {
unsigned long long ts) \
{ \
CASSERT(_flags != 0, select_proper_config); \
PMF_VALIDATE_TID(_name, tid); \
PMF_VALIDATE_TID(_name, (uint64_t)tid); \
uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \
if (((_flags) & PMF_STORE_ENABLE) != 0) \
__pmf_store_timestamp(base_addr, tid, ts); \
__pmf_store_timestamp(base_addr, \
(uint64_t)tid, ts); \
if (((_flags) & PMF_DUMP_ENABLE) != 0) \
__pmf_dump_timestamp(tid, ts); \
__pmf_dump_timestamp((uint64_t)tid, ts); \
} \
void pmf_capture_timestamp_with_cache_maint_ ## _name( \
unsigned int tid, \
unsigned long long ts) \
{ \
CASSERT(_flags != 0, select_proper_config); \
PMF_VALIDATE_TID(_name, tid); \
PMF_VALIDATE_TID(_name, (uint64_t)tid); \
uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \
if (((_flags) & PMF_STORE_ENABLE) != 0) \
__pmf_store_timestamp_with_cache_maint(base_addr, tid, ts);\
__pmf_store_timestamp_with_cache_maint( \
base_addr, (uint64_t)tid, ts); \
if (((_flags) & PMF_DUMP_ENABLE) != 0) \
__pmf_dump_timestamp(tid, ts); \
__pmf_dump_timestamp((uint64_t)tid, ts); \
}
/*
......
include/lib/smccc.h
View file @ d7b5f408
......@@ -78,8 +78,8 @@
#define SMC_64 U(1)
#define SMC_32 U(0)
#define SMC_TYPE_FAST ULL(1)
#define SMC_TYPE_YIELD ULL(0)
#define SMC_TYPE_FAST UL(1)
#define SMC_TYPE_YIELD UL(0)
#define SMC_OK ULL(0)
#define SMC_UNK -1
......@@ -112,7 +112,8 @@
/* The macro below is used to identify a valid Fast SMC call */
#define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & U(0xff))) && \
(GET_SMC_TYPE(_fid) == SMC_TYPE_FAST))
(GET_SMC_TYPE(_fid) \
== (uint32_t)SMC_TYPE_FAST))
/*
* Macro to define UUID for services. Apart from defining and initializing a
......
include/lib/xlat_tables/xlat_tables_defs.h
View file @ d7b5f408
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -74,8 +74,8 @@
* 64KB. However, only 4KB are supported at the moment.
*/
#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT
#define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT)
#define PAGE_SIZE_MASK (PAGE_SIZE - U(1))
#define PAGE_SIZE (UL(1) << PAGE_SIZE_SHIFT)
#define PAGE_SIZE_MASK (PAGE_SIZE - UL(1))
#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == U(0))
#if (ARM_ARCH_MAJOR == 7) && !ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING
......
lib/aarch64/misc_helpers.S
View file @ d7b5f408
/*
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -496,7 +496,7 @@ func fixup_gdt_reloc
/* Test if the limits are 4K aligned */
#if ENABLE_ASSERTIONS
orr x0, x0, x1
tst x0, #(PAGE_SIZE - 1)
tst x0, #(PAGE_SIZE_MASK)
ASM_ASSERT(eq)
#endif
/*
......@@ -504,7 +504,7 @@ func fixup_gdt_reloc
* Assume that this function is called within a page at the start of
* fixup region.
*/
and x2, x30, #~(PAGE_SIZE - 1)
and x2, x30, #~(PAGE_SIZE_MASK)
sub x0, x2, x6 /* Diff(S) = Current Address - Compiled Address */
adrp x1, __GOT_START__
......
lib/el3_runtime/aarch64/context_mgmt.c
View file @ d7b5f408
......@@ -710,7 +710,7 @@ void cm_write_scr_el3_bit(uint32_t security_state,
assert(ctx != NULL);
/* Ensure that the bit position is a valid one */
assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
/* Ensure that the 'value' is only a bit wide */
assert(value <= 1U);
......@@ -721,7 +721,7 @@ void cm_write_scr_el3_bit(uint32_t security_state,
*/
state = get_el3state_ctx(ctx);
scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
scr_el3 &= ~(1U << bit_pos);
scr_el3 &= ~(1UL << bit_pos);
scr_el3 |= (u_register_t)value << bit_pos;
write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
}
......
lib/psci/psci_common.c
View file @ d7b5f408
......@@ -663,7 +663,8 @@ static int psci_get_ns_ep_info(entry_point_info_t *ep,
mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? MODE_EL2 : MODE_EL1;
ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
ep->spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
} else {
mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ?
......@@ -675,7 +676,8 @@ static int psci_get_ns_ep_info(entry_point_info_t *ep,
*/
daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT;
ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif);
ep->spsr = SPSR_MODE32((uint64_t)mode, entrypoint & 0x1, ee,
daif);
}
return PSCI_E_SUCCESS;
......
lib/xlat_tables_v2/xlat_tables_utils.c
View file @ d7b5f408
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -472,7 +472,7 @@ int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
/*
* Sanity checks.
*/
for (size_t i = 0U; i < pages_count; ++i) {
for (unsigned int i = 0U; i < pages_count; ++i) {
const uint64_t *entry;
uint64_t desc, attr_index;
unsigned int level;
......@@ -497,8 +497,8 @@ int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va,
(level != XLAT_TABLE_LEVEL_MAX)) {
WARN("Address 0x%lx is not mapped at the right granularity.\n",
base_va);
WARN("Granularity is 0x%llx, should be 0x%x.\n",
(unsigned long long)XLAT_BLOCK_SIZE(level), PAGE_SIZE);
WARN("Granularity is 0x%lx, should be 0x%lx.\n",
XLAT_BLOCK_SIZE(level), PAGE_SIZE);
return -EINVAL;
}
......
plat/arm/common/arm_common.c
View file @ d7b5f408
......@@ -97,7 +97,7 @@ uint32_t arm_get_spsr_for_bl33_entry(void)
* the FIP ToC and allowing the platform to have a say as
* well.
*/
spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
return spsr;
}
#else
......
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