Merge pull request #1606 from satheesbalya-arm/sb1_2603_misra_plat

plat/arm: Fix misra warnings in platform code

include/common/interrupt_props.h

@@ -12,10 +12,10 @@
 /* Create an interrupt property descriptor from various interrupt properties */
 #define INTR_PROP_DESC(num, pri, grp, cfg) \
 	{ \
-		.intr_num = num, \
-		.intr_pri = pri, \
-		.intr_grp = grp, \
-		.intr_cfg = cfg, \
+		.intr_num = (num), \
+		.intr_pri = (pri), \
+		.intr_grp = (grp), \
+		.intr_cfg = (cfg), \
 	}
 
 typedef struct interrupt_prop {

include/drivers/arm/tzc_common.h

@@ -46,10 +46,10 @@
 
 /* Macros for allowing Non-Secure access to a region based on NSAID */
 #define TZC_REGION_ACCESS_RD(nsaid)				\
-	((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) <<		\
+	((1 << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) <<	\
 	 TZC_REGION_ACCESS_RD_EN_SHIFT)
 #define TZC_REGION_ACCESS_WR(nsaid)				\
-	((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) <<		\
+	((1 << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) <<	\
 	 TZC_REGION_ACCESS_WR_EN_SHIFT)
 #define TZC_REGION_ACCESS_RDWR(nsaid)				\
 	(TZC_REGION_ACCESS_RD(nsaid) |				\

plat/arm/board/fvp/fvp_security.c

@@ -21,6 +21,6 @@ void plat_arm_security_setup(void)
 	 * configurations, those would be configured here.
 	 */
 
-	if (get_arm_config()->flags & ARM_CONFIG_HAS_TZC)
+	if ((get_arm_config()->flags & ARM_CONFIG_HAS_TZC) != 0U)
 		arm_tzc400_setup(NULL);
 }

plat/arm/board/fvp/fvp_topology.c

@@ -16,7 +16,8 @@
 static unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 2];
 
 
-CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluster_count);
+CASSERT(((FVP_CLUSTER_COUNT > 0) && (FVP_CLUSTER_COUNT <= 256)),
+			assert_invalid_fvp_cluster_count);
 
 /*******************************************************************************
  * This function dynamically constructs the topology according to
@@ -24,7 +25,7 @@ CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluste
  ******************************************************************************/
 const unsigned char *plat_get_power_domain_tree_desc(void)
 {
-	unsigned int i;
+	int i;
 
 	/*
 	 * The highest level is the system level. The next level is constituted
@@ -60,7 +61,7 @@ int plat_core_pos_by_mpidr(u_register_t mpidr)
 	unsigned int clus_id, cpu_id, thread_id;
 
 	/* Validate affinity fields */
-	if (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) {
+	if ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) {
 		thread_id = MPIDR_AFFLVL0_VAL(mpidr);
 		cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
 		clus_id = MPIDR_AFFLVL2_VAL(mpidr);
@@ -90,5 +91,5 @@ int plat_core_pos_by_mpidr(u_register_t mpidr)
 	 * bit set.
 	 */
 	mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
-	return plat_arm_calc_core_pos(mpidr);
+	return (int) plat_arm_calc_core_pos(mpidr);
 }

plat/arm/board/fvp/include/platform_def.h

@@ -52,7 +52,7 @@
 #define PLAT_ARM_TRUSTED_DRAM_SIZE	0x02000000	/* 32 MB */
 
 /* virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME	0xc0000000
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
 
 /* No SCP in FVP */
 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE	ULL(0x0)
@@ -215,9 +215,9 @@
  */
 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \
 	ARM_G1S_IRQ_PROPS(grp), \
-	INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \
+	INTR_PROP_DESC(FVP_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 			GIC_INTR_CFG_LEVEL), \
-	INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+	INTR_PROP_DESC(FVP_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 			GIC_INTR_CFG_LEVEL)
 
 #define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)

plat/arm/board/juno/include/platform_def.h

@@ -60,7 +60,7 @@
 #define NSRAM_SIZE			0x00008000	/* 32KB */
 
 /* virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME	0xc0000000
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME	UL(0xc0000000)
 
 /*
  * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB
@@ -236,21 +236,21 @@
 	CSS_G1S_IRQ_PROPS(grp), \
 	ARM_G1S_IRQ_PROPS(grp), \
 	INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
-		grp, GIC_INTR_CFG_LEVEL), \
+		(grp), GIC_INTR_CFG_LEVEL), \
 	INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
-		grp, GIC_INTR_CFG_LEVEL), \
+		(grp), GIC_INTR_CFG_LEVEL), \
 	INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
-		grp, GIC_INTR_CFG_LEVEL), \
+		(grp), GIC_INTR_CFG_LEVEL), \
 	INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
-		grp, GIC_INTR_CFG_LEVEL), \
+		(grp), GIC_INTR_CFG_LEVEL), \
 	INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
-		grp, GIC_INTR_CFG_LEVEL), \
+		(grp), GIC_INTR_CFG_LEVEL), \
 	INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \
-		grp, GIC_INTR_CFG_LEVEL), \
+		(grp), GIC_INTR_CFG_LEVEL), \
 	INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \
-		grp, GIC_INTR_CFG_LEVEL), \
+		(grp), GIC_INTR_CFG_LEVEL), \
 	INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \
-		grp, GIC_INTR_CFG_LEVEL)
+		(grp), GIC_INTR_CFG_LEVEL)
 
 #define PLAT_ARM_G0_IRQ_PROPS(grp)	ARM_G0_IRQ_PROPS(grp)
 

plat/arm/board/juno/juno_topology.c

@@ -50,8 +50,8 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
  ******************************************************************************/
 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
 {
-	return (((mpidr) & 0x100) ? JUNO_CLUSTER1_CORE_COUNT :\
-				JUNO_CLUSTER0_CORE_COUNT);
+	return (((mpidr & (u_register_t) 0x100) != 0U) ?
+			JUNO_CLUSTER1_CORE_COUNT : JUNO_CLUSTER0_CORE_COUNT);
 }
 
 /*

plat/arm/common/arm_nor_psci_mem_protect.c

@@ -50,14 +50,14 @@ int arm_psci_read_mem_protect(int *enabled)
  ******************************************************************************/
 int arm_nor_psci_write_mem_protect(int val)
 {
-	int enable = (val != 0) ? 1 : 0;
+	unsigned long enable = (val != 0) ? 1UL : 0UL;
 
 	if (nor_unlock(PLAT_ARM_MEM_PROT_ADDR) != 0) {
 		ERROR("unlocking memory protect variable\n");
 		return -1;
 	}
 
-	if (enable == 1) {
+	if (enable == 1UL) {
 		/*
 		 * If we want to write a value different than 0
 		 * then we have to erase the full block because

plat/arm/common/arm_topology.c

@@ -29,12 +29,14 @@ int arm_check_mpidr(u_register_t mpidr)
 	pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
 #else
 	valid_mask = ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK);
-	cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
-	cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+	cluster_id = (unsigned int) ((mpidr >> MPIDR_AFF1_SHIFT) &
+						MPIDR_AFFLVL_MASK);
+	cpu_id = (unsigned int) ((mpidr >> MPIDR_AFF0_SHIFT) &
+						MPIDR_AFFLVL_MASK);
 #endif /* ARM_PLAT_MT */
 
 	mpidr &= MPIDR_AFFINITY_MASK;
-	if (mpidr & valid_mask)
+	if ((mpidr & valid_mask) != 0U)
 		return -1;
 
 	if (cluster_id >= PLAT_ARM_CLUSTER_COUNT)