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adam.huang
Arm Trusted Firmware
Commits
dc593ddc
Commit
dc593ddc
authored
Jun 10, 2019
by
Soby Mathew
Committed by
TrustedFirmware Code Review
Jun 10, 2019
Browse files
Merge "doc: Document E and W build options" into integration
parents
cb60e71e
08455b97
Changes
1
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Inline
Side-by-side
docs/getting_started/user-guide.rst
View file @
dc593ddc
...
@@ -401,6 +401,8 @@ Common build options
...
@@ -401,6 +401,8 @@ Common build options
for
development
platforms
.
``
TRUSTED_BOARD_BOOT
``
flag
must
be
set
if
this
for
development
platforms
.
``
TRUSTED_BOARD_BOOT
``
flag
must
be
set
if
this
flag
has
to
be
enabled
.
0
is
the
default
.
flag
has
to
be
enabled
.
0
is
the
default
.
-
``
E
``:
Boolean
option
to
make
warnings
into
errors
.
Default
is
1.
-
``
EL3_PAYLOAD_BASE
``:
This
option
enables
booting
an
EL3
payload
instead
of
-
``
EL3_PAYLOAD_BASE
``:
This
option
enables
booting
an
EL3
payload
instead
of
the
normal
boot
flow
.
It
must
specify
the
entry
point
address
of
the
EL3
the
normal
boot
flow
.
It
must
specify
the
entry
point
address
of
the
EL3
payload
.
Please
refer
to
the
"Booting an EL3 payload"
section
for
more
payload
.
Please
refer
to
the
"Booting an EL3 payload"
section
for
more
...
@@ -785,6 +787,10 @@ Common build options
...
@@ -785,6 +787,10 @@ Common build options
Defaults to a string formed by concatenating the version number, build type
Defaults to a string formed by concatenating the version number, build type
and build string.
and build string.
- ``W``: Warning level. Some compiler warning options of interest have been
regrouped and put in the root Makefile. This flag can take the values 0 to 3,
each level enabling more warning options. Default is 0.
- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
- ``WARMBOOT_ENABLE_DCACHE_EARLY`` : Boolean option to enable D-cache early on
the CPU after warm boot. This is applicable for platforms which do not
the CPU after warm boot. This is applicable for platforms which do not
require interconnect programming to enable cache coherency (eg: single
require interconnect programming to enable cache coherency (eg: single
...
...
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