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Commit de9d0d7c authored by Mark Dykes's avatar Mark Dykes Committed by TrustedFirmware Code Review
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Merge "Tegra: enable SDEI handling" into integration

parents 6ac1bb30 d886628d
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plat/nvidia/tegra/common/tegra_common.mk
View file @ de9d0d7c
......@@ -28,11 +28,13 @@ BL31_SOURCES += drivers/delay_timer/delay_timer.c \
${COMMON_DIR}/lib/debug/profiler.c \
${COMMON_DIR}/tegra_bl31_setup.c \
${COMMON_DIR}/tegra_delay_timer.c \
${COMMON_DIR}/tegra_ehf.c \
${COMMON_DIR}/tegra_fiq_glue.c \
${COMMON_DIR}/tegra_io_storage.c \
${COMMON_DIR}/tegra_platform.c \
${COMMON_DIR}/tegra_pm.c \
${COMMON_DIR}/tegra_sip_calls.c
${COMMON_DIR}/tegra_sip_calls.c \
${COMMON_DIR}/tegra_sdei.c
ifneq ($(ENABLE_STACK_PROTECTOR), 0)
BL31_SOURCES += ${COMMON_DIR}/tegra_stack_protector.c
......
plat/nvidia/tegra/common/tegra_ehf.c 0 → 100644
View file @ de9d0d7c
/*
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
#include <bl31/ehf.h>
/*
* Enumeration of priority levels on Tegra platforms.
*/
ehf_pri_desc_t tegra_exceptions[] = {
/* Watchdog priority */
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_TEGRA_WDT_PRIO),
#if SDEI_SUPPORT
/* Critical priority SDEI */
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_CRITICAL_PRI),
/* Normal priority SDEI */
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI),
#endif
};
/* Plug in Tegra exceptions to Exception Handling Framework. */
EHF_REGISTER_PRIORITIES(tegra_exceptions, ARRAY_SIZE(tegra_exceptions), PLAT_PRI_BITS);
plat/nvidia/tegra/common/tegra_fiq_glue.c
View file @ de9d0d7c
......@@ -26,15 +26,6 @@
/* Legacy FIQ used by earlier Tegra platforms */
#define LEGACY_FIQ_PPI_WDT 28U
/* Install priority level descriptors for each dispatcher */
ehf_pri_desc_t plat_exceptions[] = {
EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_TEGRA_WDT_PRIO),
};
/* Expose priority descriptors to Exception Handling Framework */
EHF_REGISTER_PRIORITIES(plat_exceptions, ARRAY_SIZE(plat_exceptions),
PLAT_PRI_BITS);
/*******************************************************************************
* Static variables
******************************************************************************/
......
plat/nvidia/tegra/common/tegra_sdei.c 0 → 100644
View file @ de9d0d7c
/*
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* SDEI configuration for Tegra platforms */
#include <platform_def.h>
#include <bl31/ehf.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <lib/utils_def.h>
#include <services/sdei.h>
/* Private event mappings */
static sdei_ev_map_t tegra_sdei_private[] = {
/* Event 0 definition */
SDEI_DEFINE_EVENT_0(TEGRA_SDEI_SGI_PRIVATE),
/* Dynamic private events */
SDEI_PRIVATE_EVENT(TEGRA_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC),
SDEI_PRIVATE_EVENT(TEGRA_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC),
SDEI_PRIVATE_EVENT(TEGRA_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC),
/* General purpose explicit events */
SDEI_EXPLICIT_EVENT(TEGRA_SDEI_EP_EVENT_0, SDEI_MAPF_CRITICAL),
SDEI_EXPLICIT_EVENT(TEGRA_SDEI_EP_EVENT_1, SDEI_MAPF_CRITICAL),
SDEI_EXPLICIT_EVENT(TEGRA_SDEI_EP_EVENT_2, SDEI_MAPF_CRITICAL),
SDEI_EXPLICIT_EVENT(TEGRA_SDEI_EP_EVENT_3, SDEI_MAPF_CRITICAL),
SDEI_EXPLICIT_EVENT(TEGRA_SDEI_EP_EVENT_4, SDEI_MAPF_CRITICAL),
SDEI_EXPLICIT_EVENT(TEGRA_SDEI_EP_EVENT_5, SDEI_MAPF_CRITICAL),
SDEI_EXPLICIT_EVENT(TEGRA_SDEI_EP_EVENT_6, SDEI_MAPF_CRITICAL),
SDEI_EXPLICIT_EVENT(TEGRA_SDEI_EP_EVENT_7, SDEI_MAPF_CRITICAL),
SDEI_EXPLICIT_EVENT(TEGRA_SDEI_EP_EVENT_8, SDEI_MAPF_CRITICAL),
SDEI_EXPLICIT_EVENT(TEGRA_SDEI_EP_EVENT_9, SDEI_MAPF_CRITICAL),
SDEI_EXPLICIT_EVENT(TEGRA_SDEI_EP_EVENT_10, SDEI_MAPF_CRITICAL),
SDEI_EXPLICIT_EVENT(TEGRA_SDEI_EP_EVENT_11, SDEI_MAPF_CRITICAL)
};
/* Shared event mappings */
static sdei_ev_map_t tegra_sdei_shared[] = {
/* Dynamic shared events */
SDEI_SHARED_EVENT(TEGRA_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC),
SDEI_SHARED_EVENT(TEGRA_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC),
SDEI_SHARED_EVENT(TEGRA_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
};
void plat_sdei_setup(void)
{
INFO("SDEI platform setup\n");
}
/* Export Tegra SDEI events */
REGISTER_SDEI_MAP(tegra_sdei_private, tegra_sdei_shared);
plat/nvidia/tegra/include/platform_def.h
View file @ de9d0d7c
......@@ -86,10 +86,44 @@
#define MAX_IO_DEVICES U(0)
#define MAX_IO_HANDLES U(0)
/*******************************************************************************
* Platforms macros to support SDEI
******************************************************************************/
#define TEGRA_SDEI_SGI_PRIVATE U(8)
/*******************************************************************************
* Platform macros to support exception handling framework
******************************************************************************/
#define PLAT_PRI_BITS U(3)
#define PLAT_SDEI_CRITICAL_PRI U(0x20)
#define PLAT_SDEI_NORMAL_PRI U(0x30)
#define PLAT_TEGRA_WDT_PRIO U(0x40)
/*******************************************************************************
* SDEI events
******************************************************************************/
/* SDEI dynamic private event numbers */
#define TEGRA_SDEI_DP_EVENT_0 U(100)
#define TEGRA_SDEI_DP_EVENT_1 U(101)
#define TEGRA_SDEI_DP_EVENT_2 U(102)
/* SDEI dynamic shared event numbers */
#define TEGRA_SDEI_DS_EVENT_0 U(200)
#define TEGRA_SDEI_DS_EVENT_1 U(201)
#define TEGRA_SDEI_DS_EVENT_2 U(202)
/* SDEI explicit events */
#define TEGRA_SDEI_EP_EVENT_0 U(300)
#define TEGRA_SDEI_EP_EVENT_1 U(301)
#define TEGRA_SDEI_EP_EVENT_2 U(302)
#define TEGRA_SDEI_EP_EVENT_3 U(303)
#define TEGRA_SDEI_EP_EVENT_4 U(304)
#define TEGRA_SDEI_EP_EVENT_5 U(305)
#define TEGRA_SDEI_EP_EVENT_6 U(306)
#define TEGRA_SDEI_EP_EVENT_7 U(307)
#define TEGRA_SDEI_EP_EVENT_8 U(308)
#define TEGRA_SDEI_EP_EVENT_9 U(309)
#define TEGRA_SDEI_EP_EVENT_10 U(310)
#define TEGRA_SDEI_EP_EVENT_11 U(311)
#endif /* PLATFORM_DEF_H */
plat/nvidia/tegra/platform.mk
View file @ de9d0d7c
......@@ -52,6 +52,9 @@ RELOCATE_BL32_IMAGE ?= 0
# Enable stack protection
ENABLE_STACK_PROTECTOR := strong
# Enable SDEI
SDEI_SUPPORT := 1
include plat/nvidia/tegra/common/tegra_common.mk
include ${SOC_DIR}/platform_${TARGET_SOC}.mk
......@@ -66,6 +69,7 @@ TF_CFLAGS += -Wsign-compare -nostdlib
# override with necessary libc files for the Tegra platform
override LIBC_SRCS := $(addprefix lib/libc/, \
aarch64/setjmp.S \
assert.c \
memcpy.c \
memmove.c \
......
plat/nvidia/tegra/soc/t186/plat_setup.c
View file @ de9d0d7c
......@@ -214,6 +214,8 @@ void plat_late_platform_setup(void)
/* Secure IRQs for Tegra186 */
static const interrupt_prop_t tegra186_interrupt_props[] = {
INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
......
plat/nvidia/tegra/soc/t194/plat_setup.c
View file @ de9d0d7c
......@@ -275,6 +275,8 @@ void plat_early_platform_setup(void)
/* Secure IRQs for Tegra194 */
static const interrupt_prop_t tegra194_interrupt_props[] = {
INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
......
plat/nvidia/tegra/soc/t210/plat_setup.c
View file @ de9d0d7c
......@@ -179,6 +179,8 @@ void plat_early_platform_setup(void)
/* Secure IRQs for Tegra186 */
static const interrupt_prop_t tegra210_interrupt_props[] = {
INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA210_TIMER1_IRQ, PLAT_TEGRA_WDT_PRIO,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, PLAT_TEGRA_WDT_PRIO,
......
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