mt8173: Add #error directive to prevent RESET_TO_BL31

MT8173 platform code is incompatible with RESET_TO_BL31, add #error
directive to prevent the case.

We also move mt8173_def.h and plat_private.h to include directory, and
remove some unnecessary code.

Change-Id: I47b8d0a506820a4ea1fbe8c8fb0ec6c68d88feb5
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>

plat/mediatek/mt8173/aarch64/platform_common.c

@@ -44,7 +44,7 @@ static const int cci_map[] = {
 /* Table of regions to map using the MMU.  */
 const mmap_region_t plat_mmap[] = {
 	/* for TF text, RO, RW */
-	MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE + TZRAM2_SIZE,
+	MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE,
 			MT_MEMORY | MT_RW | MT_SECURE),
 	MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
 			MT_DEVICE | MT_RW | MT_SECURE),

plat/mediatek/mt8173/bl31_plat_setup.c

@@ -146,8 +146,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 	assert(from_bl2->h.type == PARAM_BL31);
 	assert(from_bl2->h.version >= VERSION_1);
 
-	assert(((unsigned long)plat_params_from_bl2) == MT_BL31_PLAT_PARAM_VAL);
-
 	bl32_ep_info = *from_bl2->bl32_ep_info;
 	bl33_ep_info = *from_bl2->bl33_ep_info;
 }

plat/mediatek/mt8173/mt8173_def.h → plat/mediatek/mt8173/include/mt8173_def.h

@@ -28,22 +28,25 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __PLAT_DEF_H__
-#define __PLAT_DEF_H__
+#ifndef __MT8173_DEF_H__
+#define __MT8173_DEF_H__
 
-#define MT8173_PRIMARY_CPU	0x0
+#if RESET_TO_BL31
+#error "MT8173 is incompatible with RESET_TO_BL31!"
+#endif
 
-/* Special value used to verify platform parameters from BL2 to BL3-1 */
-#define MT_BL31_PLAT_PARAM_VAL	0x0f1e2d3c4b5a6978ULL
+#define MT8173_PRIMARY_CPU	0x0
 
+/* Register base address */
 #define IO_PHYS			(0x10000000)
 #define INFRACFG_AO_BASE	(IO_PHYS + 0x1000)
+#define PERI_CON_BASE		(IO_PHYS + 0x3000)
 #define GPIO_BASE		(IO_PHYS + 0x5000)
 #define SPM_BASE		(IO_PHYS + 0x6000)
 #define RGU_BASE		(IO_PHYS + 0x7000)
 #define PMIC_WRAP_BASE		(IO_PHYS + 0xD000)
 #define MCUCFG_BASE		(IO_PHYS + 0x200000)
-#define TRNG_base		(IO_PHYS + 0x20F000)
+#define TRNG_BASE		(IO_PHYS + 0x20F000)
 #define MT_GIC_BASE		(IO_PHYS + 0x220000)
 #define PLAT_MT_CCI_BASE	(IO_PHYS + 0x390000)
 
@@ -112,4 +115,4 @@
 #define MT_IRQ_SEC_SGI_6	14
 #define MT_IRQ_SEC_SGI_7	15
 
-#endif /* __PLAT_DEF_H__ */
+#endif /* __MT8173_DEF_H__ */

plat/mediatek/mt8173/include/platform_def.h

@@ -70,7 +70,21 @@
 /*******************************************************************************
  * Platform memory map related constants
  ******************************************************************************/
-/* TF txet, ro, rw, internal SRAM, Size: release: 80KB, debug: 92KB */
+/*
+ * MT8173 SRAM memory layout
+ * 0x100000 +-------------------+
+ *          | shared mem (4KB)  |
+ * 0x101000 +-------------------+
+ *          |                   |
+ *          |   BL3-1 (124KB)   |
+ *          |                   |
+ * 0x120000 +-------------------+
+ *          |  reserved (64KB)  |
+ * 0x130000 +-------------------+
+ */
+/* TF txet, ro, rw, xlat table, coherent memory ... etc.
+ * Size: release: 128KB, debug: 128KB
+ */
 #define TZRAM_BASE		(0x100000)
 #if DEBUG
 #define TZRAM_SIZE		(0x20000)
@@ -78,7 +92,7 @@
 #define TZRAM_SIZE		(0x20000)
 #endif
 
-/* xlat_table , coherence ram, 64KB */
+/* Reserved: 64KB */
 #define TZRAM2_BASE		(TZRAM_BASE + TZRAM_SIZE)
 #define TZRAM2_SIZE		(0x10000)
 

plat/mediatek/mt8173/platform.mk

@@ -32,7 +32,6 @@ MTK_PLAT		:=	plat/mediatek
 MTK_PLAT_SOC		:=	${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES		:=	-I${MTK_PLAT}/common/				\
-				-I${MTK_PLAT_SOC}/				\
 				-I${MTK_PLAT_SOC}/drivers/gpio/			\
 				-I${MTK_PLAT_SOC}/drivers/mtcmos/		\
 				-I${MTK_PLAT_SOC}/drivers/pmic/			\