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Commit e32b6228 authored by Marek Vasut's avatar Marek Vasut
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rcar_gen3: drivers: qos: Synchronize tables 



Synchronize the QoS tables with Renesas ATF release 2.0.0 .
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@gmail.com>
parent 042b4d45
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drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
View file @ e32b6228
......@@ -12,7 +12,7 @@
#include "../qos_reg.h"
#include "qos_init_e3_v10.h"
#define RCAR_QOS_VERSION "rev.0.02"
#define RCAR_QOS_VERSION "rev.0.05"
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
......@@ -134,14 +134,6 @@ void qos_init_e3_v10(void)
}
}
/* 3DG bus Leaf setting */
io_write_32(GPU_ACT_GRD, 0x00001234U);
io_write_32(GPU_ACT0, 0x00000000U);
io_write_32(GPU_ACT1, 0x00000000U);
io_write_32(GPU_ACT2, 0x00000000U);
io_write_32(GPU_ACT3, 0x00000000U);
io_write_32(GPU_ACT_GRD, 0x00000000U);
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
io_write_32(RT_ACT1, 0x00000000U);
......
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
View file @ e32b6228
......@@ -27,20 +27,20 @@ static uint64_t mstat_fix[] = {
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00a0, */ 0x000C08380000FFFFUL,
/* 0x00a8, */ 0x000C04110000FFFFUL,
/* 0x00b0, */ 0x000C04110000FFFFUL,
/* 0x00b0, */ 0x000C04150000FFFFUL,
/* 0x00b8, */ 0x0000000000000000UL,
/* 0x00c0, */ 0x000C08380000FFFFUL,
/* 0x00c8, */ 0x000C04110000FFFFUL,
/* 0x00d0, */ 0x000C04110000FFFFUL,
/* 0x00d0, */ 0x000C04150000FFFFUL,
/* 0x00d8, */ 0x0000000000000000UL,
/* 0x00e0, */ 0x0000000000000000UL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001018580000FFFFUL,
/* 0x00f8, */ 0x000C04400000FFFFUL,
/* 0x00f8, */ 0x000C084F0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x001008580000FFFFUL,
/* 0x0118, */ 0x000C19660000FFFFUL,
/* 0x0118, */ 0x000C21E40000FFFFUL,
/* 0x0120, */ 0x0000000000000000UL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
......
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
View file @ e32b6228
......@@ -27,20 +27,20 @@ static uint64_t mstat_fix[] = {
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00a0, */ 0x000C10700000FFFFUL,
/* 0x00a8, */ 0x000C08210000FFFFUL,
/* 0x00b0, */ 0x000C08210000FFFFUL,
/* 0x00b0, */ 0x000C082A0000FFFFUL,
/* 0x00b8, */ 0x0000000000000000UL,
/* 0x00c0, */ 0x000C10700000FFFFUL,
/* 0x00c8, */ 0x000C08210000FFFFUL,
/* 0x00d0, */ 0x000C08210000FFFFUL,
/* 0x00d0, */ 0x000C082A0000FFFFUL,
/* 0x00d8, */ 0x0000000000000000UL,
/* 0x00e0, */ 0x0000000000000000UL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x00102CAF0000FFFFUL,
/* 0x00f8, */ 0x000C087F0000FFFFUL,
/* 0x00f8, */ 0x000C0C9D0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x00100CAF0000FFFFUL,
/* 0x0118, */ 0x000C32CC0000FFFFUL,
/* 0x0118, */ 0x000C43C80000FFFFUL,
/* 0x0120, */ 0x0000000000000000UL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
View file @ e32b6228
......@@ -12,7 +12,8 @@
#include "../qos_reg.h"
#include "qos_init_h3_v20.h"
#define RCAR_QOS_VERSION "rev.0.19"
#define RCAR_QOS_VERSION "rev.0.20"
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
View file @ e32b6228
......@@ -12,7 +12,8 @@
#include "../qos_reg.h"
#include "qos_init_h3_v30.h"
#define RCAR_QOS_VERSION "rev.0.07"
#define RCAR_QOS_VERSION "rev.0.10"
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
......@@ -226,8 +227,6 @@ void qos_init_h3_v30(void)
io_write_32(AXI_TR3CR, 0x00010000U);
io_write_32(AXI_TR4CR, 0x00010000U);
/* 3DG bus Leaf setting */
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
io_write_32(RT_ACT1, 0x00000000U);
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
View file @ e32b6228
......@@ -36,12 +36,12 @@ static uint64_t mstat_fix[] = {
/* 0x00e0, */ 0x00100C090000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001024090000FFFFUL,
/* 0x00f8, */ 0x000C08080000FFFFUL,
/* 0x00f8, */ 0x000C100D0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x00100C090000FFFFUL,
/* 0x0118, */ 0x000C18180000FFFFUL,
/* 0x0120, */ 0x000C18180000FFFFUL,
/* 0x0118, */ 0x000C1C1B0000FFFFUL,
/* 0x0120, */ 0x000C1C1B0000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x00100C0B0000FFFFUL,
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
View file @ e32b6228
......@@ -36,12 +36,12 @@ static uint64_t mstat_fix[] = {
/* 0x00e0, */ 0x001014110000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001044110000FFFFUL,
/* 0x00f8, */ 0x000C10100000FFFFUL,
/* 0x00f8, */ 0x000C1C1A0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x001014110000FFFFUL,
/* 0x0118, */ 0x000C302F0000FFFFUL,
/* 0x0120, */ 0x000C302F0000FFFFUL,
/* 0x0118, */ 0x000C38360000FFFFUL,
/* 0x0120, */ 0x000C38360000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x001018150000FFFFUL,
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
View file @ e32b6228
......@@ -12,7 +12,8 @@
#include "../qos_reg.h"
#include "qos_init_h3n_v30.h"
#define RCAR_QOS_VERSION "rev.0.03"
#define RCAR_QOS_VERSION "rev.0.06"
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
......@@ -220,14 +221,6 @@ void qos_init_h3n_v30(void)
io_write_32(AXI_TR3CR, 0x00010000U);
io_write_32(AXI_TR4CR, 0x00010000U);
/* 3DG bus Leaf setting */
io_write_32(GPU_ACT_GRD, 0x00001234U);
io_write_32(GPU_ACT0, 0x00000000U);
io_write_32(GPU_ACT1, 0x00000000U);
io_write_32(GPU_ACT2, 0x00000000U);
io_write_32(GPU_ACT3, 0x00000000U);
io_write_32(GPU_ACT_GRD, 0x00000000U);
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
io_write_32(RT_ACT1, 0x00000000U);
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
View file @ e32b6228
......@@ -36,12 +36,12 @@ static uint64_t mstat_fix[] = {
/* 0x00e0, */ 0x00100C090000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001024090000FFFFUL,
/* 0x00f8, */ 0x000C08080000FFFFUL,
/* 0x00f8, */ 0x000C100D0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x00100C090000FFFFUL,
/* 0x0118, */ 0x000C18180000FFFFUL,
/* 0x0120, */ 0x000C18180000FFFFUL,
/* 0x0118, */ 0x000C1C1B0000FFFFUL,
/* 0x0120, */ 0x000C1C1B0000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x00100C0B0000FFFFUL,
......
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
View file @ e32b6228
......@@ -36,12 +36,12 @@ static uint64_t mstat_fix[] = {
/* 0x00e0, */ 0x001014110000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001044110000FFFFUL,
/* 0x00f8, */ 0x000C10100000FFFFUL,
/* 0x00f8, */ 0x000C1C1A0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x001014110000FFFFUL,
/* 0x0118, */ 0x000C302F0000FFFFUL,
/* 0x0120, */ 0x000C302F0000FFFFUL,
/* 0x0118, */ 0x000C38360000FFFFUL,
/* 0x0120, */ 0x000C38360000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x001018150000FFFFUL,
......
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
View file @ e32b6228
......@@ -12,7 +12,8 @@
#include "../qos_reg.h"
#include "qos_init_m3_v11.h"
#define RCAR_QOS_VERSION "rev.0.17"
#define RCAR_QOS_VERSION "rev.0.18"
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */
......
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
View file @ e32b6228
......@@ -12,7 +12,7 @@
#include "../qos_reg.h"
#include "qos_init_m3n_v10.h"
#define RCAR_QOS_VERSION "rev.0.06"
#define RCAR_QOS_VERSION "rev.0.08"
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
......@@ -198,14 +198,6 @@ void qos_init_m3n_v10(void)
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
}
/* 3DG bus Leaf setting */
io_write_32(GPU_ACT_GRD, 0x00001234U);
io_write_32(GPU_ACT0, 0x00000000U);
io_write_32(GPU_ACT1, 0x00000000U);
io_write_32(GPU_ACT2, 0x00000000U);
io_write_32(GPU_ACT3, 0x00000000U);
io_write_32(GPU_ACT_GRD, 0x00000000U);
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
io_write_32(RT_ACT1, 0x00000000U);
......
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
View file @ e32b6228
......@@ -27,11 +27,11 @@ static uint64_t mstat_fix[] = {
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00a0, */ 0x000C041D0000FFFFUL,
/* 0x00a8, */ 0x000C04090000FFFFUL,
/* 0x00b0, */ 0x000C04090000FFFFUL,
/* 0x00b0, */ 0x000C040B0000FFFFUL,
/* 0x00b8, */ 0x0000000000000000UL,
/* 0x00c0, */ 0x000C041D0000FFFFUL,
/* 0x00c8, */ 0x000C04090000FFFFUL,
/* 0x00d0, */ 0x000C04090000FFFFUL,
/* 0x00d0, */ 0x000C040B0000FFFFUL,
/* 0x00d8, */ 0x0000000000000000UL,
/* 0x00e0, */ 0x0000000000000000UL,
/* 0x00e8, */ 0x0000000000000000UL,
......
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
View file @ e32b6228
......@@ -27,11 +27,11 @@ static uint64_t mstat_fix[] = {
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00a0, */ 0x000C08390000FFFFUL,
/* 0x00a8, */ 0x000C04110000FFFFUL,
/* 0x00b0, */ 0x000C04110000FFFFUL,
/* 0x00b0, */ 0x000C04150000FFFFUL,
/* 0x00b8, */ 0x0000000000000000UL,
/* 0x00c0, */ 0x000C08390000FFFFUL,
/* 0x00c8, */ 0x000C04110000FFFFUL,
/* 0x00d0, */ 0x000C04110000FFFFUL,
/* 0x00d0, */ 0x000C04150000FFFFUL,
/* 0x00d8, */ 0x0000000000000000UL,
/* 0x00e0, */ 0x0000000000000000UL,
/* 0x00e8, */ 0x0000000000000000UL,
......
drivers/staging/renesas/rcar/qos/qos_common.h
View file @ e32b6228
......@@ -9,6 +9,15 @@
#define RCAR_REF_DEFAULT (0U)
/* define used for get_refperiod. */
/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */
/* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */
#define REFPERIOD_CYCLE ((126 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
#else /* REF option */
#define REFPERIOD_CYCLE ((252 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
#endif
#if (RCAR_LSI == RCAR_E3)
/* define used for E3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
......@@ -19,7 +28,7 @@
#define OPERATING_FREQ_E3 (266U) /* MHz */
#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 -1U)
#define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) /* unit:ns */
/* #define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) */ /* unit:ns */
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
......
drivers/staging/renesas/rcar/qos/qos_init.c
View file @ e32b6228
......@@ -238,6 +238,7 @@ void rcar_qos_init(void)
#endif
}
#if !(RCAR_LSI == RCAR_E3)
uint32_t get_refperiod(void)
{
uint32_t refperiod = QOSWT_WTSET0_CYCLE;
......@@ -254,11 +255,9 @@ uint32_t get_refperiod(void)
case PRR_PRODUCT_11:
break;
case PRR_PRODUCT_20:
refperiod = QOSWT_WTSET0_CYCLE_H3_20;
break;
case PRR_PRODUCT_30:
default:
refperiod = QOSWT_WTSET0_CYCLE_H3_30;
refperiod = REFPERIOD_CYCLE;
break;
}
break;
......@@ -267,7 +266,7 @@ uint32_t get_refperiod(void)
switch (reg & PRR_CUT_MASK) {
case PRR_PRODUCT_30:
default:
refperiod = QOSWT_WTSET0_CYCLE_H3N;
refperiod = REFPERIOD_CYCLE;
break;
}
break;
......@@ -277,21 +276,16 @@ uint32_t get_refperiod(void)
switch (reg & PRR_CUT_MASK) {
case PRR_PRODUCT_10:
break;
case PRR_PRODUCT_20: /* M3 Cut 11 */
case PRR_PRODUCT_20: /* M3 Cut 11 */
default:
refperiod = QOSWT_WTSET0_CYCLE_M3_11;
refperiod = REFPERIOD_CYCLE;
break;
}
break;
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
case PRR_PRODUCT_M3N:
refperiod = QOSWT_WTSET0_CYCLE_M3N;
break;
#endif
#if (RCAR_LSI == RCAR_E3)
case PRR_PRODUCT_E3:
refperiod = QOSWT_WTSET0_CYCLE_E3;
refperiod = REFPERIOD_CYCLE;
break;
#endif
default:
......@@ -302,28 +296,25 @@ uint32_t get_refperiod(void)
/* H3 Cut 10 */
#elif RCAR_LSI_CUT == RCAR_CUT_11
/* H3 Cut 11 */
#elif RCAR_LSI_CUT == RCAR_CUT_20
/* H3 Cut 20 */
refperiod = QOSWT_WTSET0_CYCLE_H3_20;
#else
/* H3 Cut 20 */
/* H3 Cut 30 or later */
refperiod = QOSWT_WTSET0_CYCLE_H3_30;
refperiod = REFPERIOD_CYCLE;
#endif
#elif RCAR_LSI == RCAR_H3N
/* H3N Cut 30 or later */
refperiod = QOSWT_WTSET0_CYCLE_H3N;
refperiod = REFPERIOD_CYCLE;
#elif RCAR_LSI == RCAR_M3
#if RCAR_LSI_CUT == RCAR_CUT_10
/* M3 Cut 10 */
#else
/* M3 Cut 11 or later */
refperiod = QOSWT_WTSET0_CYCLE_M3_11;
refperiod = REFPERIOD_CYCLE;
#endif
#elif RCAR_LSI == RCAR_M3N /* for M3N */
refperiod = QOSWT_WTSET0_CYCLE_M3N;
#elif RCAR_LSI == RCAR_E3 /* for E3 */
refperiod = QOSWT_WTSET0_CYCLE_E3;
refperiod = REFPERIOD_CYCLE;
#endif
return refperiod;
}
#endif
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