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Commit e4e6c4be authored by Eleanor Bonnici's avatar Eleanor Bonnici Committed by Jeenu Viswambharan
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CPU: Make shifted constants unsigned 


In order to avoid Undefined behavior, left operand in left-shift
expressions needs to be unsigned, and of sufficient size. The safest and
most consistent approach is to use unsigned long long type.

Change-Id: I9612f16a6e6ea4c7df62a02497d862abf19b8e1b
Signed-off-by: default avatarEleanor Bonnici <Eleanor.bonnici@arm.com>
parent afb33432
master v2.5 v2.5-rc1 v2.5-rc0 v2.4 v2.4-rc2 v2.4-rc1 v2.4-rc0 v2.3 v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.2 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.1 v2.1-rc1 v2.1-rc0 v2.0 v2.0-rc0 v1.6 v1.6-rc1 v1.6-rc0 v1.5 v1.5-rc3 v1.5-rc2 v1.5-rc1 v1.5-rc0 arm_cca_v0.2 arm_cca_v0.1
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with 63 additions and 59 deletions
+63 -59
include/lib/cpus/aarch32/cortex_a57.h
View file @ e4e6c4be
......@@ -6,6 +6,7 @@
#ifndef __CORTEX_A57_H__
#define __CORTEX_A57_H__
#include <utils_def.h>
/* Cortex-A57 midr for revision 0 */
#define CORTEX_A57_MIDR 0x410FD070
......@@ -24,13 +25,13 @@
******************************************************************************/
#define CORTEX_A57_ECTLR p15, 1, c15
#define CORTEX_A57_ECTLR_SMP_BIT (1 << 6)
#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)
#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
......@@ -42,26 +43,26 @@
******************************************************************************/
#define CORTEX_A57_ACTLR p15, 0, c15
#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (1 << 59)
#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (1 << 54)
#define CORTEX_A57_ACTLR_DIS_OVERREAD (1 << 52)
#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (1 << 49)
#define CORTEX_A57_ACTLR_DCC_AS_DCCI (1 << 44)
#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (1 << 38)
#define CORTEX_A57_ACTLR_DIS_STREAMING (3 << 27)
#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (3 << 25)
#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (1 << 4)
#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)
#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)
#define CORTEX_A57_ACTLR_DIS_OVERREAD (ULL(1) << 52)
#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
#define CORTEX_A57_ACTLR_DCC_AS_DCCI (ULL(1) << 44)
#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38)
#define CORTEX_A57_ACTLR_DIS_STREAMING (ULL(3) << 27)
#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (ULL(3) << 25)
#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
/*******************************************************************************
* L2 Extended Control register specific definitions.
......@@ -69,7 +70,7 @@
#define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3
#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0
#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (0x7 << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (ULL(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
......
include/lib/cpus/aarch32/cortex_a72.h
View file @ e4e6c4be
......@@ -6,6 +6,7 @@
#ifndef __CORTEX_A72_H__
#define __CORTEX_A72_H__
#include <utils_def.h>
/* Cortex-A72 midr for revision 0 */
#define CORTEX_A72_MIDR 0x410FD080
......@@ -13,42 +14,42 @@
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A72_ECTLR p15, 1, c15
#define CORTEX_A72_ECTLR p15, 1, c15
#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6)
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CORTEX_A72_MERRSR p15, 2, c15
#define CORTEX_A72_MERRSR p15, 2, c15
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CORTEX_A72_ACTLR p15, 0, c15
#define CORTEX_A72_ACTLR p15, 0, c15
#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49)
#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44)
#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
#define CORTEX_A72_ACTLR_DCC_AS_DCCI (ULL(1) << 44)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CORTEX_A72_L2MERRSR p15, 3, c15
#define CORTEX_A72_L2MERRSR p15, 3, c15
#endif /* __CORTEX_A72_H__ */
include/lib/cpus/aarch64/cortex_a57.h
View file @ e4e6c4be
......@@ -6,6 +6,7 @@
#ifndef __CORTEX_A57_H__
#define __CORTEX_A57_H__
#include <utils_def.h>
/* Cortex-A57 midr for revision 0 */
#define CORTEX_A57_MIDR U(0x410FD070)
......@@ -55,15 +56,15 @@
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2
#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2
#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21)
#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21)
/*******************************************************************************
* L2 Extended Control register specific definitions.
......
include/lib/cpus/aarch64/cortex_a72.h
View file @ e4e6c4be
......@@ -6,49 +6,50 @@
#ifndef __CORTEX_A72_H__
#define __CORTEX_A72_H__
#include <utils_def.h>
/* Cortex-A72 midr for revision 0 */
#define CORTEX_A72_MIDR 0x410FD080
#define CORTEX_A72_MIDR 0x410FD080
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1
#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1
#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6)
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2
#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CORTEX_A72_ACTLR_EL1 S3_1_C15_C2_0
#define CORTEX_A72_ACTLR_EL1 S3_1_C15_C2_0
#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49)
#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44)
#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)
#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
#define CORTEX_A72_ACTLR_DCC_AS_DCCI (ULL(1) << 44)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
#endif /* __CORTEX_A72_H__ */
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