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Commit e5f3812e authored by Madhukar Pappireddy's avatar Madhukar Pappireddy Committed by TrustedFirmware Code Review
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Merge "cpus: denver: disable cycle counter when event counting is prohibited" into integration

parents 02383c28 c5c1af0d
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lib/cpus/aarch64/denver.S
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/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -33,6 +34,12 @@ vector_base workaround_bpflush_runtime_exceptions ...@@ -33,6 +34,12 @@ vector_base workaround_bpflush_runtime_exceptions
.macro apply_workaround .macro apply_workaround
stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
/* Disable cycle counter when event counting is prohibited */
mrs x1, pmcr_el0
orr x0, x1, #PMCR_EL0_DP_BIT
msr pmcr_el0, x0
isb
/* ------------------------------------------------- /* -------------------------------------------------
* A new write-only system register where a write of * A new write-only system register where a write of
* 1 to bit 0 will cause the indirect branch predictor * 1 to bit 0 will cause the indirect branch predictor
......
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