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Commit e9cd36f5 authored by Manish Pandey's avatar Manish Pandey Committed by TrustedFirmware Code Review
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Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into integration 

* changes:
  renesas: rzg: Add support to identify EK874 RZ/G2E board
  drivers: renesas: common: watchdog: Add support for RZ/G2E
  drivers: renesas: rzg: Add QoS support for RZ/G2E
  drivers: renesas: rzg: Add PFC support for RZ/G2E
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
  renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board
  drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC
  drivers: renesas: rzg: Add QoS support for RZ/G2N
  drivers: renesas: rzg: Add PFC support for RZ/G2N
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
  renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board
  drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC
  drivers: renesas: rzg: Add QoS support for RZ/G2H
  drivers: renesas: rzg: Add PFC support for RZ/G2H
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
  drivers: renesas: rzg: Switch using common ddr code
  drivers: renesas: ddr: Move to common
parents d8dc8c9e bcf43f04
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drivers/renesas/rcar/ddr/ddr.mk deleted 100644 → 0
View file @ d8dc8c9e
#
# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq (${RCAR_LSI},${RCAR_E3})
include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c
else ifeq (${RCAR_LSI},${RCAR_D3})
include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
else ifeq (${RCAR_LSI},${RCAR_V3M})
include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
else
include drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c
endif
drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk deleted 100644 → 0
View file @ d8dc8c9e
#
# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq (${RCAR_LSI},${RCAR_E3})
BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
else ifeq (${RCAR_LSI},${RCAR_D3})
BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
else
BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
endif
drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk deleted 100644 → 0
View file @ d8dc8c9e
#
# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
drivers/renesas/rzg/board/board.c
View file @ e9cd36f5
/*
* Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -13,7 +13,15 @@
#include "rcar_def.h"
#ifndef BOARD_DEFAULT
#if (RCAR_LSI == RZ_G2H)
#define BOARD_DEFAULT (BOARD_HIHOPE_RZ_G2H << BOARD_CODE_SHIFT)
#elif (RCAR_LSI == RZ_G2N)
#define BOARD_DEFAULT (BOARD_HIHOPE_RZ_G2N << BOARD_CODE_SHIFT)
#elif (RCAR_LSI == RZ_G2E)
#define BOARD_DEFAULT (BOARD_EK874_RZ_G2E << BOARD_CODE_SHIFT)
#else
#define BOARD_DEFAULT (BOARD_HIHOPE_RZ_G2M << BOARD_CODE_SHIFT)
#endif /* RCAR_LSI == RZ_G2H */
#endif /* BOARD_DEFAULT */
#define BOARD_CODE_MASK (0xF8U)
......@@ -27,9 +35,15 @@
#define GP5_25_BIT (0x01U << 25)
#define HM_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define HH_ID HM_ID
#define HN_ID { 0x20U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define EK_ID HM_ID
const char *g_board_tbl[] = {
[BOARD_HIHOPE_RZ_G2M] = "HiHope RZ/G2M",
[BOARD_HIHOPE_RZ_G2H] = "HiHope RZ/G2H",
[BOARD_HIHOPE_RZ_G2N] = "HiHope RZ/G2N",
[BOARD_EK874_RZ_G2E] = "EK874 RZ/G2E",
[BOARD_UNKNOWN] = "unknown"
};
......@@ -38,8 +52,14 @@ void rzg_get_board_type(uint32_t *type, uint32_t *rev)
static uint8_t board_id = BOARD_ID_UNKNOWN;
const uint8_t board_tbl[][8] = {
[BOARD_HIHOPE_RZ_G2M] = HM_ID,
[BOARD_HIHOPE_RZ_G2H] = HH_ID,
[BOARD_HIHOPE_RZ_G2N] = HN_ID,
[BOARD_EK874_RZ_G2E] = EK_ID,
};
uint32_t reg, boardInfo;
uint32_t reg;
#if (RCAR_LSI != RZ_G2E)
uint32_t boardInfo;
#endif /* RCAR_LSI == RZ_G2E */
if (board_id == BOARD_ID_UNKNOWN) {
board_id = BOARD_DEFAULT;
......@@ -50,15 +70,28 @@ void rzg_get_board_type(uint32_t *type, uint32_t *rev)
if (*type >= ARRAY_SIZE(board_tbl)) {
/* no revision information, set Rev0.0. */
*rev = 0;
return;
}
reg = mmio_read_32(RCAR_PRR);
#if (RCAR_LSI == RZ_G2E)
if (reg & RCAR_MINOR_MASK) {
*rev = 0x30U;
} else {
*rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
}
#else
if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) {
*rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
} else {
reg = mmio_read_32(RCAR_PRR);
if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) {
reg = mmio_read_32(GPIO_INDT5);
if (reg & GP5_25_BIT) {
*rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
} else {
boardInfo = mmio_read_32(GPIO_INDT5) &
(GP5_19_BIT | GP5_21_BIT);
boardInfo = reg & (GP5_19_BIT | GP5_21_BIT);
*rev = (((boardInfo & GP5_19_BIT) >> 14) |
((boardInfo & GP5_21_BIT) >> 17)) + 0x30U;
}
}
#endif /* RCAR_LSI == RZ_G2E */
}
drivers/renesas/rzg/board/board.h
View file @ e9cd36f5
/*
* Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -9,6 +9,9 @@
enum rzg2_board_id {
BOARD_HIHOPE_RZ_G2M = 0,
BOARD_HIHOPE_RZ_G2H,
BOARD_HIHOPE_RZ_G2N,
BOARD_EK874_RZ_G2E,
BOARD_UNKNOWN
};
......
drivers/renesas/rzg/ddr/boot_init_dram.h deleted 100644 → 0
View file @ d8dc8c9e
/*
* Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BOOT_INIT_DRAM_H
#define BOOT_INIT_DRAM_H
extern int32_t rzg_dram_init(void);
#define INITDRAM_OK 0
#define INITDRAM_NG 0xffffffff
#define INITDRAM_ERR_I 0xffffffff
#define INITDRAM_ERR_O 0xfffffffe
#define INITDRAM_ERR_T 0xfffffff0
#endif /* BOOT_INIT_DRAM_H */
drivers/renesas/rzg/ddr/ddr.mk deleted 100644 → 0
View file @ d8dc8c9e
#
# Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
include drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c deleted 100644 → 0
View file @ d8dc8c9e
This diff is collapsed.
drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c deleted 100644 → 0
View file @ d8dc8c9e
/*
* Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define BOARDNUM 2
#define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
static uint32_t _board_judge(uint32_t prr_product);
static uint32_t boardcnf_get_brd_type(uint32_t prr_product)
{
return _board_judge(prr_product);
}
#else /* BOARD_JUDGE_AUTO */
static uint32_t boardcnf_get_brd_type(void)
{
return 1U;
}
#endif /* BOARD_JUDGE_AUTO */
#define DDR_FAST_INIT
struct _boardcnf_ch {
uint8_t ddr_density[CS_CNT];
uint64_t ca_swap;
uint16_t dqs_swap;
uint32_t dq_swap[SLICE_CNT];
uint8_t dm_swap[SLICE_CNT];
uint16_t wdqlvl_patt[16];
int8_t cacs_adj[16];
int8_t dm_adj_w[SLICE_CNT];
int8_t dq_adj_w[SLICE_CNT * 8U];
int8_t dm_adj_r[SLICE_CNT];
int8_t dq_adj_r[SLICE_CNT * 8U];
};
struct _boardcnf {
uint8_t phyvalid;
uint8_t dbi_en;
uint16_t cacs_dly;
int16_t cacs_dly_adj;
uint16_t dqdm_dly_w;
uint16_t dqdm_dly_r;
struct _boardcnf_ch ch[DRAM_CH_CNT];
};
#define WDQLVL_PAT {\
0x00AA,\
0x0055,\
0x00AA,\
0x0155,\
0x01CC,\
0x0133,\
0x00CC,\
0x0033,\
0x00F0,\
0x010F,\
0x01F0,\
0x010F,\
0x00F0,\
0x00F0,\
0x000F,\
0x010F}
static const struct _boardcnf boardcnfs[BOARDNUM] = {
{
/* boardcnf[0] HopeRun HiHope RZ/G2M 16Gbit/1rank/2ch board with G2M SoC */
.phyvalid = 0x03,
.dbi_en = 0x01,
.cacs_dly = 0x02c0,
.cacs_dly_adj = 0,
.dqdm_dly_w = 0x0300,
.dqdm_dly_r = 0x00a0,
.ch = {
{
{0x04, 0xff},
0x00345201U,
0x3201,
{0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
{
{0x04, 0xff},
0x00302154U,
0x2310,
{0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
},
/* boardcnf[1] HopeRun HiHope RZ/G2M 8Gbit/2rank/2ch board with G2M SoC */
{
0x03,
0x01,
0x02c0,
0,
0x0300,
0x00a0,
{
{
{0x02, 0x02},
0x00345201U,
0x3201,
{0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
{
{0x02, 0x02},
0x00302154U,
0x2310,
{0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
}
};
void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
{
uint32_t md;
md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3U;
switch (md) {
case 0x0U:
*clk = 50U;
*div = 3U;
break;
case 0x1U:
*clk = 60U;
*div = 3U;
break;
case 0x2U:
*clk = 75U;
*div = 3U;
break;
case 0x3U:
*clk = 100U;
*div = 3U;
break;
default:
break;
}
(void)brd;
}
void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
{
uint32_t md;
md = (mmio_read_32(RST_MODEMR) >> 17U) & 0x5U;
md = (md | (md >> 1U)) & 0x3U;
switch (md) {
case 0x0U:
*mbps = 3200U;
*div = 1U;
break;
case 0x1U:
*mbps = 2800U;
*div = 1U;
break;
case 0x2U:
*mbps = 2400U;
*div = 1U;
break;
case 0x3U:
*mbps = 1600U;
*div = 1U;
break;
default:
break;
}
(void)brd;
}
#define _def_REFPERIOD 1890
#define M3_SAMPLE_TT_A84 0xB866CC10U, 0x3B250421U
#define M3_SAMPLE_TT_A85 0xB866CC10U, 0x3AA50421U
#define M3_SAMPLE_TT_A86 0xB866CC10U, 0x3AA48421U
#define M3_SAMPLE_FF_B45 0xB866CC10U, 0x3AB00C21U
#define M3_SAMPLE_FF_B49 0xB866CC10U, 0x39B10C21U
#define M3_SAMPLE_FF_B56 0xB866CC10U, 0x3AAF8C21U
#define M3_SAMPLE_SS_E24 0xB866CC10U, 0x3BA39421U
#define M3_SAMPLE_SS_E28 0xB866CC10U, 0x3C231421U
#define M3_SAMPLE_SS_E32 0xB866CC10U, 0x3C241421U
static const uint32_t termcode_by_sample[20][3] = {
{ M3_SAMPLE_TT_A84, 0x000158D5U },
{ M3_SAMPLE_TT_A85, 0x00015955U },
{ M3_SAMPLE_TT_A86, 0x00015955U },
{ M3_SAMPLE_FF_B45, 0x00015690U },
{ M3_SAMPLE_FF_B49, 0x00015753U },
{ M3_SAMPLE_FF_B56, 0x00015793U },
{ M3_SAMPLE_SS_E24, 0x00015996U },
{ M3_SAMPLE_SS_E28, 0x000159D7U },
{ M3_SAMPLE_SS_E32, 0x00015997U },
{ 0xFFFFFFFFU, 0xFFFFFFFFU, 0x0001554FU}
};
#ifdef BOARD_JUDGE_AUTO
/* Board detect function */
#define GPIO_INDT5 0xE605500CU
#define LPDDR4_2RANK (0x01U << 25U)
static uint32_t _board_judge(uint32_t prr_product)
{
uint32_t boardInfo;
uint32_t boardid = 1U;
if (prr_product == PRR_PRODUCT_M3) {
if ((mmio_read_32(PRR) & PRR_CUT_MASK) != RCAR_M3_CUT_VER11) {
boardInfo = mmio_read_32(GPIO_INDT5);
if ((boardInfo & LPDDR4_2RANK) == 0U) {
boardid = 0U;
}
}
}
return boardid;
}
#endif /* BOARD_JUDGE_AUTO */
drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h deleted 100644 → 0
View file @ d8dc8c9e
/*
* Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef RZG_BOOT_INIT_DRAM_REGDEF_H
#define RZG_BOOT_INIT_DRAM_REGDEF_H
#define RCAR_DDR_VERSION "rev.0.40"
#define DRAM_CH_CNT 0x04U
#define SLICE_CNT 0x04U
#define CS_CNT 0x02U
/* order : CS0A, CS0B, CS1A, CS1B */
#define CSAB_CNT (CS_CNT * 2U)
/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
#define CHAB_CNT (DRAM_CH_CNT * 2)
/* pll setting */
#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
/* for ddr density setting */
#define DBMEMCONF_REG(d3, row, bank, col, dw) \
(((d3) << 30U) | ((row) << 24U) | ((bank) << 16U) | ((col) << 8U) | (dw))
#define DBMEMCONF_REGD(density) \
(DBMEMCONF_REG((density) % 2U, ((density) + 1U) / \
2U + (29U - 3U - 10U - 2U), 3U, 10U, 2U))
#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
/* refresh mode */
#define DBSC_REFINTS (0x0U)
/* system registers */
#define CPG_FRQCRB (CPG_BASE + 0x0004U)
#define CPG_PLLECR (CPG_BASE + 0x00D0U)
#define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
#define CPG_SRCR4 (CPG_BASE + 0x00BCU)
#define CPG_PLL3CR (CPG_BASE + 0x00DCU)
#define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
#define CPG_FRQCRD (CPG_BASE + 0x00E4U)
#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
#define CPG_CPGWPR (CPG_BASE + 0x0900U)
#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
#define CPG_FRQCRB_KICK_BIT BIT(31)
#define CPG_PLLECR_PLL3E_BIT BIT(3)
#define CPG_PLLECR_PLL3ST_BIT BIT(11)
#define CPG_ZB3CKCR_ZB3ST_BIT BIT(11)
#define RST_BASE (0xE6160000U)
#define RST_MODEMR (RST_BASE + 0x0060U)
#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x))
/* DBSC registers */
#include "ddr_regs.h"
#define DBSC_DBMONCONF4 0xE6793010U
#define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch))
#define DBSC_PLL_LOCK_0 0xE6794054U
#define DBSC_PLL_LOCK_1 0xE6794154U
#define DBSC_PLL_LOCK_2 0xE6794254U
#define DBSC_PLL_LOCK_3 0xE6794354U
/* STAT registers */
#define MSTAT_SL_INIT 0xE67E8000U
#define MSTAT_REF_ARS 0xE67E8004U
#define MSTATQ_STATQC 0xE67E8008U
#define MSTATQ_WTENABLE 0xE67E8030U
#define MSTATQ_WTREFRESH 0xE67E8034U
#define MSTATQ_WTSETTING0 0xE67E8038U
#define MSTATQ_WTSETTING1 0xE67E803CU
#define QOS_BASE1 (0xE67F0000U)
#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
/* other module */
#define THS1_THCTR 0xE6198020U
#define THS1_TEMP 0xE6198028U
#endif /* RZG_BOOT_INIT_DRAM_REGDEF_H */
drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h deleted 100644 → 0
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drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h deleted 100644 → 0
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drivers/renesas/rzg/ddr/dram_sub_func.h deleted 100644 → 0
View file @ d8dc8c9e
/*
* Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef DRAM_SUB_FUNC_H
#define DRAM_SUB_FUNC_H
#define DRAM_UPDATE_STATUS_ERR -1
#define DRAM_BOOT_STATUS_COLD 0
#define DRAM_BOOT_STATUS_WARM 1
#endif /* DRAM_SUB_FUNC_H */
drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c 0 → 100644
View file @ e9cd36f5
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drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.h 0 → 100644
View file @ e9cd36f5
/*
* Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PFC_INIT_G2E_H
#define PFC_INIT_G2E_H
void pfc_init_g2e(void);
#endif /* PFC_INIT_G2E_H */
drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c 0 → 100644
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drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.h 0 → 100644
View file @ e9cd36f5
/*
* Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PFC_INIT_G2H_H
#define PFC_INIT_G2H_H
void pfc_init_g2h(void);
#endif /* PFC_INIT_G2H_H */
drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c 0 → 100644
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drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.h 0 → 100644
View file @ e9cd36f5
/*
* Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PFC_INIT_G2N_H
#define PFC_INIT_G2N_H
void pfc_init_g2n(void);
#endif /* PFC_INIT_G2N_H */
drivers/renesas/rzg/pfc/pfc.mk
View file @ e9cd36f5
#
# Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
# Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq (${RCAR_LSI},${RCAR_AUTO})
BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
BL2_SOURCES += drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
BL2_SOURCES += drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
BL2_SOURCES += drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
else ifdef RCAR_LSI_CUT_COMPAT
ifeq (${RCAR_LSI},${RZ_G2M})
BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
endif
ifeq (${RCAR_LSI},${RZ_G2H})
BL2_SOURCES += drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
endif
ifeq (${RCAR_LSI},${RZ_G2N})
BL2_SOURCES += drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
endif
ifeq (${RCAR_LSI},${RZ_G2E})
BL2_SOURCES += drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
endif
else
ifeq (${RCAR_LSI},${RZ_G2M})
BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
endif
ifeq (${RCAR_LSI},${RZ_G2H})
BL2_SOURCES += drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
endif
ifeq (${RCAR_LSI},${RZ_G2N})
BL2_SOURCES += drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
endif
ifeq (${RCAR_LSI},${RZ_G2E})
BL2_SOURCES += drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
endif
endif
BL2_SOURCES += drivers/renesas/rzg/pfc/pfc_init.c
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