Merge changes Ib9c82b85,Ib348e097,I4dc315e4,I58a8ce44,Iebc03361, ... into integration

* changes:
  plat: marvell: armada: a8k: add OP-TEE OS MMU tables
  drivers: marvell: add support for mapping the entire LLC to SRAM
  plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms
  plat: marvell: armada: reduce memory size reserved for FIP image
  plat: marvell: armada: platform definitions cleanup
  plat: marvell: armada: a8k: check CCU window state before loading MSS BL2
  drivers: marvell: add CCU driver API for window state checking
  drivers: marvell: align and extend llc macros
  plat: marvell: a8k: move address config of cp1/2 to BL2
  plat: marvell: armada: re-enable BL32_BASE definition
  plat: marvell: a8k: extend includes to take advantage of the phy_porting_layer
  marvell: comphy: initialize common phy selector for AP mode
  marvell: comphy: update rx_training procedure
  plat: marvell: armada: configure amb for all CPs
  plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs

plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c

@@ -10,6 +10,7 @@
 #include <common/bl_common.h>
 #include <common/debug.h>
 #include <drivers/marvell/ccu.h>
+#include <drivers/marvell/mochi/ap_setup.h>
 #include <drivers/marvell/mochi/cp110_setup.h>
 #include <lib/mmio.h>
 
@@ -18,9 +19,6 @@
 
 #include "mss_scp_bootloader.h"
 
-/* IO windows configuration */
-#define IOW_GCR_OFFSET		(0x70)
-
 /* MSS windows configuration */
 #define MSS_AEBR(base)			(base + 0x160)
 #define MSS_AIBR(base)			(base + 0x164)
@@ -51,7 +49,7 @@ struct addr_map_win ccu_mem_map[] = {
  */
 static int bl2_plat_mmap_init(void)
 {
-	int cfg_num, win_id, cfg_idx;
+	int cfg_num, win_id, cfg_idx, cp;
 
 	cfg_num =  ARRAY_SIZE(ccu_mem_map);
 
@@ -65,20 +63,29 @@ static int bl2_plat_mmap_init(void)
 	 * Do not touch CCU window 0,
 	 * it's used for the internal registers access
 	 */
-	for (cfg_idx = 0, win_id = 1; cfg_idx < cfg_num; cfg_idx++, win_id++) {
+	for (cfg_idx = 0, win_id = 1;
+	     (win_id < MVEBU_CCU_MAX_WINS) && (cfg_idx < cfg_num); win_id++) {
+		/* Skip already enabled CCU windows */
+		if (ccu_is_win_enabled(MVEBU_AP0, win_id))
+			continue;
 		/* Enable required CCU windows */
 		ccu_win_check(&ccu_mem_map[cfg_idx]);
 		ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id);
+		cfg_idx++;
 	}
 
-	/* Set the default target id to PIDI */
-	mmio_write_32(MVEBU_IO_WIN_BASE(MVEBU_AP0) + IOW_GCR_OFFSET, PIDI_TID);
+	/* Config address for each cp other than cp0 */
+	for (cp = 1; cp < CP_COUNT; cp++)
+		update_cp110_default_win(cp);
 
-	/* Open AMB bridge required for MG access */
-	cp110_amb_init(MVEBU_CP_REGS_BASE(0));
+	/* There is need to configure IO_WIN windows again to overwrite
+	 * temporary configuration done during update_cp110_default_win
+	 */
+	init_io_win(MVEBU_AP0);
 
-	if (CP_COUNT == 2)
-		cp110_amb_init(MVEBU_CP_REGS_BASE(1));
+	/* Open AMB bridge required for MG access */
+	for (cp = 0; cp < CP_COUNT; cp++)
+		cp110_amb_init(MVEBU_CP_REGS_BASE(cp));
 
 	return 0;
 }

plat/marvell/armada/a8k/common/plat_bl31_setup.c

@@ -116,21 +116,12 @@ void bl31_plat_arch_setup(void)
 		marvell_bl31_plat_arch_setup();
 
 	for (cp = 0; cp < CP_COUNT; cp++) {
-		if (cp >= 1)
-			update_cp110_default_win(cp);
-
 		cp110_init(MVEBU_CP_REGS_BASE(cp),
 			   STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP));
 
 		marvell_bl31_mpp_init(cp);
 	}
 
-	/*
-	 * There is need to configure IO_WIN windows again to overwrite
-	 * temporary configuration done during update_cp110_default_win
-	 */
-	init_io_win(MVEBU_AP0);
-
 	for (cp = 1; cp < CP_COUNT; cp++)
 		mci_link_tune(cp - 1);
 

plat/marvell/armada/common/aarch64/marvell_helpers.S

@@ -185,7 +185,7 @@ func disable_sram
 
 	/* Invalidate all ways */
 	ldr	w1, =LLC_WAY_MASK
-	ldr	x0, =MASTER_L2X0_INV_WAY
+	ldr	x0, =MASTER_LLC_INV_WAY
 	str	w1, [x0]
 
 	/* Finally disable LLC */

plat/marvell/armada/common/marvell_common.mk

@@ -16,8 +16,21 @@ SEPARATE_CODE_AND_RODATA	:= 1
 # flag to switch from PLL to ARO
 ARO_ENABLE			:= 0
 $(eval $(call add_define,ARO_ENABLE))
+
+# Convert LLC to secure SRAM
+LLC_SRAM			:= 0
+$(eval $(call add_define,LLC_SRAM))
+
 # Enable/Disable LLC
+ifeq (${LLC_SRAM}, 0)
 LLC_ENABLE			:= 1
+else
+# When LLC_SRAM=1, the entire LLC converted to SRAM and enabled at BL1.
+# All existing cases activating LLC at BL31 stage should be disabled.
+# The below assignment does not allow changing the LLC_ENABLE
+# value in the command line.
+LLC_ENABLE			= 0
+endif
 $(eval $(call add_define,LLC_ENABLE))
 
 include lib/xlat_tables_v2/xlat_tables.mk