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Commit f0209639 authored by Biju Das's avatar Biju Das
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plat: renesas: rcar: include: Code cleanup 



This patch fixes checkpatch warnings and replaces TAB with
space after #define macros.
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
parent 157c4fca
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plat/renesas/rcar/include/platform_def.h
View file @ f0209639
/* /*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -29,20 +29,20 @@ ...@@ -29,20 +29,20 @@
/* Size of cacheable stacks */ /* Size of cacheable stacks */
#if IMAGE_BL1 #if IMAGE_BL1
#if TRUSTED_BOARD_BOOT #if TRUSTED_BOARD_BOOT
#define PLATFORM_STACK_SIZE U(0x1000) #define PLATFORM_STACK_SIZE U(0x1000)
#else #else
#define PLATFORM_STACK_SIZE U(0x440) #define PLATFORM_STACK_SIZE U(0x440)
#endif #endif
#elif IMAGE_BL2 #elif IMAGE_BL2
#if TRUSTED_BOARD_BOOT #if TRUSTED_BOARD_BOOT
#define PLATFORM_STACK_SIZE U(0x1000) #define PLATFORM_STACK_SIZE U(0x1000)
#else #else
#define PLATFORM_STACK_SIZE U(0x400) #define PLATFORM_STACK_SIZE U(0x400)
#endif #endif
#elif IMAGE_BL31 #elif IMAGE_BL31
#define PLATFORM_STACK_SIZE U(0x400) #define PLATFORM_STACK_SIZE U(0x400)
#elif IMAGE_BL32 #elif IMAGE_BL32
#define PLATFORM_STACK_SIZE U(0x440) #define PLATFORM_STACK_SIZE U(0x440)
#endif #endif
#define BL332_IMAGE_ID (NS_BL2U_IMAGE_ID + 1) #define BL332_IMAGE_ID (NS_BL2U_IMAGE_ID + 1)
...@@ -97,11 +97,13 @@ ...@@ -97,11 +97,13 @@
#define MAX_IO_DEVICES U(3) #define MAX_IO_DEVICES U(3)
#define MAX_IO_HANDLES U(4) #define MAX_IO_HANDLES U(4)
/******************************************************************************* /*
******************************************************************************
* BL2 specific defines. * BL2 specific defines.
******************************************************************************/ ******************************************************************************
/* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth. */ * size plus a little space for growth.
*/
#define RCAR_SYSRAM_BASE U(0xE6300000) #define RCAR_SYSRAM_BASE U(0xE6300000)
#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) #if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
#define BL2_LIMIT U(0xE6320000) #define BL2_LIMIT U(0xE6320000)
...@@ -121,17 +123,19 @@ ...@@ -121,17 +123,19 @@
#endif #endif
#define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE) #define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
/******************************************************************************* /*
******************************************************************************
* BL31 specific defines. * BL31 specific defines.
******************************************************************************/ ******************************************************************************
/* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL3-1 debug size plus a little space for growth. */ * current BL3-1 debug size plus a little space for growth.
*/
#define BL31_BASE (RCAR_TRUSTED_SRAM_BASE) #define BL31_BASE (RCAR_TRUSTED_SRAM_BASE)
#define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE + \ #define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE + \
RCAR_TRUSTED_SRAM_SIZE) RCAR_TRUSTED_SRAM_SIZE)
#define RCAR_BL31_LOG_BASE (0x44040000) #define RCAR_BL31_LOG_BASE (0x44040000)
#define RCAR_BL31_SDRAM_BTM (RCAR_BL31_LOG_BASE + 0x14000) #define RCAR_BL31_SDRAM_BTM (RCAR_BL31_LOG_BASE + 0x14000)
#define RCAR_BL31_LOG_SIZE (RCAR_BL31_SDRAM_BTM - RCAR_BL31_LOG_BASE) #define RCAR_BL31_LOG_SIZE (RCAR_BL31_SDRAM_BTM - RCAR_BL31_LOG_BASE)
#define BL31_SRAM_BASE (DEVICE_SRAM_BASE) #define BL31_SRAM_BASE (DEVICE_SRAM_BASE)
#define BL31_SRAM_LIMIT (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE) #define BL31_SRAM_LIMIT (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
...@@ -176,7 +180,7 @@ ...@@ -176,7 +180,7 @@
* Declarations and constants to access the mailboxes safely. Each mailbox is * Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only * aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external * to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache * caches. Such alignment ensures that two mailboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters & * line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of * get written while being protected by different locks causing corruption of
* a valid mailbox address. * a valid mailbox address.
......
plat/renesas/rcar/include/rcar_def.h
View file @ f0209639
/* /*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -33,13 +33,13 @@ ...@@ -33,13 +33,13 @@
#define DRAM1_SIZE U(0x80000000) #define DRAM1_SIZE U(0x80000000)
#define DRAM1_NS_BASE (DRAM1_BASE + U(0x10000000)) #define DRAM1_NS_BASE (DRAM1_BASE + U(0x10000000))
#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_NS_BASE) #define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_NS_BASE)
#define DRAM_40BIT_BASE ULL(0x0400000000) #define DRAM_40BIT_BASE ULL(0x0400000000)
#define DRAM_40BIT_SIZE ULL(0x0400000000) #define DRAM_40BIT_SIZE ULL(0x0400000000)
#define DRAM_PROTECTED_BASE ULL(0x43F00000) #define DRAM_PROTECTED_BASE ULL(0x43F00000)
#define DRAM_40BIT_PROTECTED_BASE ULL(0x0403F00000) #define DRAM_40BIT_PROTECTED_BASE ULL(0x0403F00000)
#define DRAM_PROTECTED_SIZE ULL(0x03F00000) #define DRAM_PROTECTED_SIZE ULL(0x03F00000)
#define RCAR_BL31_CRASH_BASE U(0x4403F000) #define RCAR_BL31_CRASH_BASE U(0x4403F000)
#define RCAR_BL31_CRASH_SIZE U(0x00001000) #define RCAR_BL31_CRASH_SIZE U(0x00001000)
/* Entrypoint mailboxes */ /* Entrypoint mailboxes */
#define MBOX_BASE RCAR_SHARED_MEM_BASE #define MBOX_BASE RCAR_SHARED_MEM_BASE
#define MBOX_SIZE 0x200 #define MBOX_SIZE 0x200
...@@ -47,15 +47,19 @@ ...@@ -47,15 +47,19 @@
#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE) #define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
#define BOOT_KIND_BASE (RCAR_SHARED_MEM_BASE + \ #define BOOT_KIND_BASE (RCAR_SHARED_MEM_BASE + \
RCAR_SHARED_MEM_SIZE - 0x100) RCAR_SHARED_MEM_SIZE - 0x100)
/* The number of regions like RO(code), coherent and data required by /*
* different BL stages which need to be mapped in the MMU */ * The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU
*/
#if USE_COHERENT_MEM #if USE_COHERENT_MEM
#define RCAR_BL_REGIONS (3) #define RCAR_BL_REGIONS (3)
#else #else
#define RCAR_BL_REGIONS (2) #define RCAR_BL_REGIONS (2)
#endif #endif
/* The RCAR_MAX_MMAP_REGIONS depend on the number of entries in rcar_mmap[] /*
* defined for each BL stage in rcar_common.c. */ * The RCAR_MAX_MMAP_REGIONS depends on the number of entries in rcar_mmap[]
* defined for each BL stage in rcar_common.c.
*/
#if IMAGE_BL2 #if IMAGE_BL2
#define RCAR_MMAP_ENTRIES (9) #define RCAR_MMAP_ENTRIES (9)
#endif #endif
...@@ -73,24 +77,24 @@ ...@@ -73,24 +77,24 @@
/* BL33 */ /* BL33 */
#define NS_IMAGE_OFFSET (DRAM1_BASE + U(0x09000000)) #define NS_IMAGE_OFFSET (DRAM1_BASE + U(0x09000000))
/* BL31 */ /* BL31 */
#define RCAR_DEVICE_BASE DEVICE_RCAR_BASE #define RCAR_DEVICE_BASE DEVICE_RCAR_BASE
#define RCAR_DEVICE_SIZE (0x1A000000) #define RCAR_DEVICE_SIZE (0x1A000000)
#define RCAR_LOG_RES_SIZE (512/8) #define RCAR_LOG_RES_SIZE (64)
#define RCAR_LOG_HEADER_SIZE (16) #define RCAR_LOG_HEADER_SIZE (16)
#define RCAR_LOG_OTHER_SIZE (RCAR_LOG_HEADER_SIZE + \ #define RCAR_LOG_OTHER_SIZE (RCAR_LOG_HEADER_SIZE + \
RCAR_LOG_RES_SIZE) RCAR_LOG_RES_SIZE)
#define RCAR_BL31_LOG_MAX (RCAR_BL31_LOG_SIZE - \ #define RCAR_BL31_LOG_MAX (RCAR_BL31_LOG_SIZE - \
RCAR_LOG_OTHER_SIZE) RCAR_LOG_OTHER_SIZE)
#define RCAR_CRASH_STACK RCAR_BL31_CRASH_BASE #define RCAR_CRASH_STACK RCAR_BL31_CRASH_BASE
#define AARCH64_SPACE_BASE ULL(0x00000000000) #define AARCH64_SPACE_BASE ULL(0x00000000000)
#define AARCH64_SPACE_SIZE ULL(0x10000000000) #define AARCH64_SPACE_SIZE ULL(0x10000000000)
/* CCI related constants */ /* CCI related constants */
#define CCI500_BASE U(0xF1200000) #define CCI500_BASE U(0xF1200000)
#define CCI500_CLUSTER0_SL_IFACE_IX (2) #define CCI500_CLUSTER0_SL_IFACE_IX (2)
#define CCI500_CLUSTER1_SL_IFACE_IX (3) #define CCI500_CLUSTER1_SL_IFACE_IX (3)
#define CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3 (1) #define CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3 (1)
#define CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3 (2) #define CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3 (2)
#define RCAR_CCI_BASE CCI500_BASE #define RCAR_CCI_BASE CCI500_BASE
/* GIC */ /* GIC */
#define RCAR_GICD_BASE U(0xF1010000) #define RCAR_GICD_BASE U(0xF1010000)
#define RCAR_GICR_BASE U(0xF1010000) #define RCAR_GICR_BASE U(0xF1010000)
...@@ -106,47 +110,47 @@ ...@@ -106,47 +110,47 @@
#define ARM_IRQ_SEC_SGI_5 U(13) #define ARM_IRQ_SEC_SGI_5 U(13)
#define ARM_IRQ_SEC_SGI_6 U(14) #define ARM_IRQ_SEC_SGI_6 U(14)
#define ARM_IRQ_SEC_SGI_7 U(15) #define ARM_IRQ_SEC_SGI_7 U(15)
#define ARM_IRQ_SEC_RPC U(70) #define ARM_IRQ_SEC_RPC U(70)
#define ARM_IRQ_SEC_TIMER U(166) #define ARM_IRQ_SEC_TIMER U(166)
#define ARM_IRQ_SEC_TIMER_UP U(171) #define ARM_IRQ_SEC_TIMER_UP U(171)
#define ARM_IRQ_SEC_WDT U(173) #define ARM_IRQ_SEC_WDT U(173)
#define ARM_IRQ_SEC_CRYPT U(102) #define ARM_IRQ_SEC_CRYPT U(102)
#define ARM_IRQ_SEC_CRYPT_SecPKA U(97) #define ARM_IRQ_SEC_CRYPT_SecPKA U(97)
#define ARM_IRQ_SEC_CRYPT_PubPKA U(98) #define ARM_IRQ_SEC_CRYPT_PubPKA U(98)
/* Timer control */ /* Timer control */
#define RCAR_CNTC_BASE U(0xE6080000) #define RCAR_CNTC_BASE U(0xE6080000)
/* Reset */ /* Reset */
#define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */ #define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */
#define RCAR_MODEMR U(0xE6160060) /* Mode pin */ #define RCAR_MODEMR U(0xE6160060) /* Mode pin */
#define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */ #define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */
#define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */ #define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */
#define RCAR_SRESCR U(0xE6160110) /* Soft Power On Reset */ #define RCAR_SRESCR U(0xE6160110) /* Soft Power On Reset */
#define RCAR_CA53WUPCR U(0xE6151010) /* Wake-up control A53 */ #define RCAR_CA53WUPCR U(0xE6151010) /* Wake-up control A53 */
#define RCAR_CA57WUPCR U(0xE6152010) /* Wake-up control A57 */ #define RCAR_CA57WUPCR U(0xE6152010) /* Wake-up control A57 */
#define RCAR_CA53PSTR U(0xE6151040) /* Power status A53 */ #define RCAR_CA53PSTR U(0xE6151040) /* Power status A53 */
#define RCAR_CA57PSTR U(0xE6152040) /* Power status A57 */ #define RCAR_CA57PSTR U(0xE6152040) /* Power status A57 */
#define RCAR_CA53CPU0CR U(0xE6151100) /* CPU control A53 */ #define RCAR_CA53CPU0CR U(0xE6151100) /* CPU control A53 */
#define RCAR_CA57CPU0CR U(0xE6152100) /* CPU control A57 */ #define RCAR_CA57CPU0CR U(0xE6152100) /* CPU control A57 */
#define RCAR_CA53CPUCMCR U(0xE6151184) /* Common power A53 */ #define RCAR_CA53CPUCMCR U(0xE6151184) /* Common power A53 */
#define RCAR_CA57CPUCMCR U(0xE6152184) /* Common power A57 */ #define RCAR_CA57CPUCMCR U(0xE6152184) /* Common power A57 */
#define RCAR_WUPMSKCA57 U(0xE6180014) /* Wake-up mask A57 */ #define RCAR_WUPMSKCA57 U(0xE6180014) /* Wake-up mask A57 */
#define RCAR_WUPMSKCA53 U(0xE6180018) /* Wake-up mask A53 */ #define RCAR_WUPMSKCA53 U(0xE6180018) /* Wake-up mask A53 */
/* SYSC */ /* SYSC */
#define RCAR_PWRSR3 U(0xE6180140) /* Power stat A53-SCU */ #define RCAR_PWRSR3 U(0xE6180140) /* Power stat A53-SCU */
#define RCAR_PWRSR5 U(0xE61801C0) /* Power stat A57-SCU */ #define RCAR_PWRSR5 U(0xE61801C0) /* Power stat A57-SCU */
#define RCAR_SYSCIER U(0xE618000C) /* Interrupt enable */ #define RCAR_SYSCIER U(0xE618000C) /* Interrupt enable */
#define RCAR_SYSCIMR U(0xE6180010) /* Interrupt mask */ #define RCAR_SYSCIMR U(0xE6180010) /* Interrupt mask */
#define RCAR_SYSCSR U(0xE6180000) /* SYSC status */ #define RCAR_SYSCSR U(0xE6180000) /* SYSC status */
#define RCAR_PWRONCR3 U(0xE618014C) /* Power resume A53-SCU */ #define RCAR_PWRONCR3 U(0xE618014C) /* Power resume A53-SCU */
#define RCAR_PWRONCR5 U(0xE61801CC) /* Power resume A57-SCU */ #define RCAR_PWRONCR5 U(0xE61801CC) /* Power resume A57-SCU */
#define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutof A53-SCU */ #define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutoff A53-SCU */
#define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutof A57-SCU */ #define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutoff A57-SCU */
#define RCAR_PWRER3 U(0xE6180154) /* shutoff/resume error */ #define RCAR_PWRER3 U(0xE6180154) /* shutoff/resume error */
#define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */ #define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */
#define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */ #define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */
#define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */ #define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */
/* Product register */ /* Product register */
#define RCAR_PRR U(0xFFF00044) #define RCAR_PRR U(0xFFF00044)
#define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */ #define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */
#define RCAR_MAJOR_MASK U(0x000000F0) #define RCAR_MAJOR_MASK U(0x000000F0)
#define RCAR_MINOR_MASK U(0x0000000F) #define RCAR_MINOR_MASK U(0x0000000F)
...@@ -198,39 +202,39 @@ ...@@ -198,39 +202,39 @@
/* Memory mapped Generic timer interfaces */ /* Memory mapped Generic timer interfaces */
#define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE #define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE
/* MODEMR PLL masks and bitfield values */ /* MODEMR PLL masks and bitfield values */
#define CHECK_MD13_MD14 U(0x6000) #define CHECK_MD13_MD14 U(0x6000)
#define MD14_MD13_TYPE_0 U(0x0000) /* MD14=0 MD13=0 */ #define MD14_MD13_TYPE_0 U(0x0000) /* MD14=0 MD13=0 */
#define MD14_MD13_TYPE_1 U(0x2000) /* MD14=0 MD13=1 */ #define MD14_MD13_TYPE_1 U(0x2000) /* MD14=0 MD13=1 */
#define MD14_MD13_TYPE_2 U(0x4000) /* MD14=1 MD13=0 */ #define MD14_MD13_TYPE_2 U(0x4000) /* MD14=1 MD13=0 */
#define MD14_MD13_TYPE_3 U(0x6000) /* MD14=1 MD13=1 */ #define MD14_MD13_TYPE_3 U(0x6000) /* MD14=1 MD13=1 */
/* Frequency of EXTAL(Hz) */ /* Frequency of EXTAL(Hz) */
#define EXTAL_MD14_MD13_TYPE_0 U(8333300) /* MD14=0 MD13=0 */ #define EXTAL_MD14_MD13_TYPE_0 U(8333300) /* MD14=0 MD13=0 */
#define EXTAL_MD14_MD13_TYPE_1 U(10000000) /* MD14=0 MD13=1 */ #define EXTAL_MD14_MD13_TYPE_1 U(10000000) /* MD14=0 MD13=1 */
#define EXTAL_MD14_MD13_TYPE_2 U(12500000) /* MD14=1 MD13=0 */ #define EXTAL_MD14_MD13_TYPE_2 U(12500000) /* MD14=1 MD13=0 */
#define EXTAL_MD14_MD13_TYPE_3 U(16666600) /* MD14=1 MD13=1 */ #define EXTAL_MD14_MD13_TYPE_3 U(16666600) /* MD14=1 MD13=1 */
#define EXTAL_SALVATOR_XS U(8320000) /* Salvator-XS */ #define EXTAL_SALVATOR_XS U(8320000) /* Salvator-XS */
#define EXTAL_EBISU U(24000000) /* Ebisu */ #define EXTAL_EBISU U(24000000) /* Ebisu */
#define EXTAL_DRAAK U(24000000) /* Draak */ #define EXTAL_DRAAK U(24000000) /* Draak */
/* CPG write protect registers */ /* CPG write protect registers */
#define CPGWPR_PASSWORD (0x5A5AFFFFU) #define CPGWPR_PASSWORD (0x5A5AFFFFU)
#define CPGWPCR_PASSWORD (0xA5A50000U) #define CPGWPCR_PASSWORD (0xA5A50000U)
/* CA5x Debug Resource control registers */ /* CA5x Debug Resource control registers */
#define CPG_CA57DBGRCR (CPG_BASE + 0x2180U) #define CPG_CA57DBGRCR (CPG_BASE + 0x2180U)
#define CPG_CA53DBGRCR (CPG_BASE + 0x1180U) #define CPG_CA53DBGRCR (CPG_BASE + 0x1180U)
#define DBGCPUPREN ((uint32_t)1U << 19U) #define DBGCPUPREN ((uint32_t)1U << 19U)
#define CPG_PLL0CR (CPG_BASE + 0x00D8U) #define CPG_PLL0CR (CPG_BASE + 0x00D8U)
#define CPG_PLL2CR (CPG_BASE + 0x002CU) #define CPG_PLL2CR (CPG_BASE + 0x002CU)
#define CPG_PLL4CR (CPG_BASE + 0x01F4U) #define CPG_PLL4CR (CPG_BASE + 0x01F4U)
#define CPG_CPGWPCR (CPG_BASE + 0x0904U) #define CPG_CPGWPCR (CPG_BASE + 0x0904U)
/* RST Registers */ /* RST Registers */
#define RST_BASE (0xE6160000U) #define RST_BASE (0xE6160000U)
#define RST_WDTRSTCR (RST_BASE + 0x0054U) #define RST_WDTRSTCR (RST_BASE + 0x0054U)
#define RST_MODEMR (RST_BASE + 0x0060U) #define RST_MODEMR (RST_BASE + 0x0060U)
#define WDTRSTCR_PASSWORD (0xA55A0000U) #define WDTRSTCR_PASSWORD (0xA55A0000U)
#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U) #define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)
/* MFIS Registers */ /* MFIS Registers */
#define MFISWPCNTR_PASSWORD (0xACCE0000U) #define MFISWPCNTR_PASSWORD (0xACCE0000U)
#define MFISWPCNTR (0xE6260900U) #define MFISWPCNTR (0xE6260900U)
/* IPMMU registers */ /* IPMMU registers */
#define IPMMU_MM_BASE (0xE67B0000U) #define IPMMU_MM_BASE (0xE67B0000U)
#define IPMMUMM_IMSCTLR (IPMMU_MM_BASE + 0x0500U) #define IPMMUMM_IMSCTLR (IPMMU_MM_BASE + 0x0500U)
...@@ -263,8 +267,8 @@ ...@@ -263,8 +267,8 @@
#define IPMMU_DS1_BASE (0xE7740000U) #define IPMMU_DS1_BASE (0xE7740000U)
#define IPMMUDS1_IMSCTLR (IPMMU_DS1_BASE + 0x0500U) #define IPMMUDS1_IMSCTLR (IPMMU_DS1_BASE + 0x0500U)
/* ARMREG registers */ /* ARMREG registers */
#define P_ARMREG_SEC_CTRL (0xE62711F0U) #define P_ARMREG_SEC_CTRL (0xE62711F0U)
#define P_ARMREG_SEC_CTRL_PROT (0x00000001U) #define P_ARMREG_SEC_CTRL_PROT (0x00000001U)
/* MIDR */ /* MIDR */
#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT) #define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT) #define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
...@@ -279,28 +283,28 @@ ...@@ -279,28 +283,28 @@
#define RCAR_COLD_BOOT (0x00U) #define RCAR_COLD_BOOT (0x00U)
#define RCAR_WARM_BOOT (0x01U) #define RCAR_WARM_BOOT (0x01U)
#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR #if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
#define KEEP10_MAGIC (0x55U) #define KEEP10_MAGIC (0x55U)
#endif #endif
/* lossy registers */ /* lossy registers */
#define LOSSY_PARAMS_BASE (0x47FD7000U) #define LOSSY_PARAMS_BASE (0x47FD7000U)
#define AXI_DCMPAREACRA0 (0xE6784100U) #define AXI_DCMPAREACRA0 (0xE6784100U)
#define AXI_DCMPAREACRB0 (0xE6784104U) #define AXI_DCMPAREACRB0 (0xE6784104U)
#define LOSSY_ENABLE (0x80000000U) #define LOSSY_ENABLE (0x80000000U)
#define LOSSY_DISABLE (0x00000000U) #define LOSSY_DISABLE (0x00000000U)
#define LOSSY_FMT_YUVPLANAR (0x00000000U) #define LOSSY_FMT_YUVPLANAR (0x00000000U)
#define LOSSY_FMT_YUV422INTLV (0x20000000U) #define LOSSY_FMT_YUV422INTLV (0x20000000U)
#define LOSSY_FMT_ARGB8888 (0x40000000U) #define LOSSY_FMT_ARGB8888 (0x40000000U)
#define LOSSY_ST_ADDR0 (0x54000000U) #define LOSSY_ST_ADDR0 (0x54000000U)
#define LOSSY_END_ADDR0 (0x57000000U) #define LOSSY_END_ADDR0 (0x57000000U)
#define LOSSY_FMT0 LOSSY_FMT_YUVPLANAR #define LOSSY_FMT0 LOSSY_FMT_YUVPLANAR
#define LOSSY_ENA_DIS0 LOSSY_ENABLE #define LOSSY_ENA_DIS0 LOSSY_ENABLE
#define LOSSY_ST_ADDR1 0x0U #define LOSSY_ST_ADDR1 0x0U
#define LOSSY_END_ADDR1 0x0U #define LOSSY_END_ADDR1 0x0U
#define LOSSY_FMT1 LOSSY_FMT_ARGB8888 #define LOSSY_FMT1 LOSSY_FMT_ARGB8888
#define LOSSY_ENA_DIS1 LOSSY_DISABLE #define LOSSY_ENA_DIS1 LOSSY_DISABLE
#define LOSSY_ST_ADDR2 0x0U #define LOSSY_ST_ADDR2 0x0U
#define LOSSY_END_ADDR2 0x0U #define LOSSY_END_ADDR2 0x0U
#define LOSSY_FMT2 LOSSY_FMT_YUV422INTLV #define LOSSY_FMT2 LOSSY_FMT_YUV422INTLV
#define LOSSY_ENA_DIS2 LOSSY_DISABLE #define LOSSY_ENA_DIS2 LOSSY_DISABLE
#endif /* RCAR_DEF_H */ #endif /* RCAR_DEF_H */
plat/renesas/rcar/include/rcar_private.h
View file @ f0209639
/* /*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -7,12 +7,12 @@ ...@@ -7,12 +7,12 @@
#ifndef RCAR_PRIVATE_H #ifndef RCAR_PRIVATE_H
#define RCAR_PRIVATE_H #define RCAR_PRIVATE_H
#include <platform_def.h>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <lib/bakery_lock.h> #include <lib/bakery_lock.h>
#include <lib/el3_runtime/cpu_data.h> #include <lib/el3_runtime/cpu_data.h>
#include <platform_def.h>
typedef volatile struct mailbox { typedef volatile struct mailbox {
unsigned long value __aligned(CACHE_WRITEBACK_GRANULE); unsigned long value __aligned(CACHE_WRITEBACK_GRANULE);
} mailbox_t; } mailbox_t;
...@@ -62,17 +62,18 @@ typedef struct rcar_cpu_data { ...@@ -62,17 +62,18 @@ typedef struct rcar_cpu_data {
*/ */
#define rcar_lock_init(_lock_arg) #define rcar_lock_init(_lock_arg)
#define rcar_lock_get(_lock_arg) \ #define rcar_lock_get(_lock_arg) \
bakery_lock_get(_lock_arg, \ bakery_lock_get(_lock_arg, \
CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET) CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET)
#define rcar_lock_release(_lock_arg) \ #define rcar_lock_release(_lock_arg) \
bakery_lock_release(_lock_arg, \ bakery_lock_release(_lock_arg, \
CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET) CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET)
/* Ensure that the size of the RCAR specific per-cpu data structure and the size /*
* Ensure that the size of the RCAR specific per-cpu data structure and the size
* of the memory allocated in generic per-cpu data for the platform are the same * of the memory allocated in generic per-cpu data for the platform are the same
*/ */
CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(rcar_cpu_data_t), CASSERT(sizeof(rcar_cpu_data_t) == PLAT_PCPU_DATA_SIZE,
rcar_pcpu_data_size_mismatch); rcar_pcpu_data_size_mismatch);
#endif #endif
/* /*
...@@ -84,7 +85,7 @@ void rcar_configure_mmu_el3(unsigned long total_base, ...@@ -84,7 +85,7 @@ void rcar_configure_mmu_el3(unsigned long total_base,
#if USE_COHERENT_MEM #if USE_COHERENT_MEM
, unsigned long coh_start, unsigned long coh_limit , unsigned long coh_start, unsigned long coh_limit
#endif #endif
); );
void rcar_setup_topology(void); void rcar_setup_topology(void);
void rcar_cci_disable(void); void rcar_cci_disable(void);
......
plat/renesas/rcar/include/registers/lifec_registers.h
View file @ f0209639
/* /*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -7,138 +7,138 @@ ...@@ -7,138 +7,138 @@
#ifndef LIFEC_REGISTERS_H #ifndef LIFEC_REGISTERS_H
#define LIFEC_REGISTERS_H #define LIFEC_REGISTERS_H
#define LIFEC_SEC_BASE (0xE6110000U) #define LIFEC_SEC_BASE (0xE6110000U)
#define SEC_SRC (LIFEC_SEC_BASE + 0x0008U) #define SEC_SRC (LIFEC_SEC_BASE + 0x0008U)
#define SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U) #define SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U)
#define SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U) #define SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U)
#define SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U) #define SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U)
#define SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU) #define SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU)
#define SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U) #define SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U)
#define SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU) #define SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU)
#define SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U) #define SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U)
#define SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U) #define SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U)
#define SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U) #define SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U)
#define SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU) #define SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU)
#define SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U) #define SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U)
#define SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U) #define SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U)
#define SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U) #define SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U)
#define SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU) #define SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU)
#define SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U) #define SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U)
#define SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U) #define SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U)
#define SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U) #define SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U)
#define SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU) #define SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU)
#define SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U) #define SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U)
#define SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U) #define SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U)
#define SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U) #define SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U)
#define SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU) #define SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU)
#define SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U) #define SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U)
#define SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U) #define SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U)
#define SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U) #define SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U)
#define SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU) #define SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU)
#define SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U) #define SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U)
#define SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U) #define SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U)
#define SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U) #define SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U)
#define SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU) #define SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU)
#define SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U) #define SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U)
#define SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U) #define SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U)
#define SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U) #define SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U)
#define SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU) #define SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU)
#define SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U) #define SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U)
#define SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U) #define SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U)
#define SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U) #define SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U)
#define SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU) #define SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU)
#define SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U) #define SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U)
#define SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U) #define SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U)
#define SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U) #define SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U)
#define SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU) #define SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU)
#define SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U) #define SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U)
#define SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U) #define SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U)
#define SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U) #define SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U)
#define SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU) #define SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU)
#define SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U) #define SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U)
#define SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U) #define SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U)
#define SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U) #define SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U)
#define SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU) #define SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU)
#define SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U) #define SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U)
#define SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U) #define SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U)
#define SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U) #define SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U)
#define SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU) #define SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU)
#define SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U) #define SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U)
#define SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U) #define SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U)
#define SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U) #define SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U)
#define SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU) #define SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU)
#define SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U) #define SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U)
#define SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U) #define SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U)
#define SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U) #define SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U)
#define SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU) #define SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU)
#define SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U) #define SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U)
#define SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U) #define SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U)
#define SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U) #define SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U)
#define SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU) #define SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU)
#define SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U) #define SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U)
#define SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U) #define SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U)
#define SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U) #define SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U)
#define SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU) #define SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU)
#define SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U) #define SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U)
#define SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U) #define SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U)
#define LIFEC_SAFE_BASE (0xE6120000U) #define LIFEC_SAFE_BASE (0xE6120000U)
#define SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U) #define SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U)
#define SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU) #define SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU)
#define SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U) #define SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U)
#define SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U) #define SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U)
#define SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U) #define SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U)
#define SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU) #define SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU)
#define SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U) #define SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U)
#define SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U) #define SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U)
#define SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U) #define SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U)
#define SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU) #define SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU)
#define SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U) #define SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U)
#define SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U) #define SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U)
#define SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U) #define SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U)
#define SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU) #define SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU)
#define SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U) #define SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U)
#define SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U) #define SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U)
#define SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U) #define SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U)
#define SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU) #define SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU)
#define SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U) #define SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U)
#define SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U) #define SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U)
#define SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U) #define SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U)
#define SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU) #define SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU)
#define SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U) #define SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U)
#define SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U) #define SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U)
#define SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U) #define SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U)
#define SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU) #define SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU)
#define SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U) #define SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U)
#define SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U) #define SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U)
#define SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U) #define SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U)
#define SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU) #define SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU)
#define SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U) #define SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U)
#define SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U) #define SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U)
#define SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U) #define SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U)
#define SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU) #define SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU)
#define SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U) #define SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U)
#define SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U) #define SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U)
#define SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U) #define SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U)
#define SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU) #define SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU)
#define SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U) #define SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U)
#define SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U) #define SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U)
#define SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U) #define SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U)
#define SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU) #define SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU)
#define SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U) #define SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U)
#define SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U) #define SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U)
#define SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U) #define SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U)
#define SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU) #define SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU)
#define SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U) #define SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U)
#define SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U) #define SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U)
#define SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U) #define SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U)
#define SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU) #define SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU)
#define SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U) #define SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U)
#define SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U) #define SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U)
#define SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U) #define SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U)
#define SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU) #define SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU)
#define SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U) #define SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U)
#define SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U) #define SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U)
#endif /* LIFEC_REGISTERS_H */ #endif /* LIFEC_REGISTERS_H */
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