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Commit f0b1864f authored by Manish Pandey's avatar Manish Pandey Committed by TrustedFirmware Code Review
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Merge "fdts: n1sdp: DTS file for single-chip and multi-chip environment." into integration

parents 4db3a887 000653b4
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fdts/n1sdp-multi-chip.dts 0 → 100644
View file @ f0b1864f
// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
/*
* Copyright (c) 2019-2020, Arm Limited.
*/
#include "n1sdp-single-chip.dts"
/ {
cpus {
cpu4@100000000 {
compatible = "arm,neoverse-n1";
reg = <0x1 0x0>;
device_type = "cpu";
enable-method = "psci";
numa-node-id = <1>;
};
cpu5@100000100 {
compatible = "arm,neoverse-n1";
reg = <0x1 0x00000100>;
device_type = "cpu";
enable-method = "psci";
numa-node-id = <1>;
};
cpu6@100010000 {
compatible = "arm,neoverse-n1";
reg = <0x1 0x00010000>;
device_type = "cpu";
enable-method = "psci";
numa-node-id = <1>;
};
cpu7@100010100 {
compatible = "arm,neoverse-n1";
reg = <0x1 0x00010100>;
device_type = "cpu";
enable-method = "psci";
numa-node-id = <1>;
};
};
/* Remote N1SDP board address is mapped at offset 4TB.
* First DRAM Bank of remote N1SDP board is mapped at 4TB + 2GB.
*/
memory@40080000000 {
device_type = "memory";
reg = <0x00000400 0x80000000 0x0 0x80000000>,
<0x00000480 0x80000000 0x3 0x80000000>;
numa-node-id = <1>;
};
distance-map {
compatible = "numa-distance-map-v1";
distance-matrix = <0 0 10>,
<0 1 20>,
<1 1 10>;
};
};
&gic {
#redistributor-regions = <2>;
reg = <0x0 0x30000000 0 0x10000>, /* GICD */
<0x0 0x300c0000 0 0x80000>, /* GICR */
<0x400 0x300c0000 0 0x80000>; /* GICR */
};
fdts/n1sdp-single-chip.dts 0 → 100644
View file @ f0b1864f
// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
/*
* Copyright (c) 2019-2020, Arm Limited.
*/
/dts-v1/;
#include "n1sdp.dtsi"
/ {
model = "Arm Neoverse N1 System Development Platform";
compatible = "arm,neoverse-n1-sdp", "arm,neoverse-n1-soc";
aliases {
serial0 = &soc_uart0;
};
chosen {
stdout-path = "soc_uart0:115200n8";
};
/* This configuration assumes that standard setup with two DIMM modules.
* In the first 2GB of DRAM bank the top 16MB are reserved by firmware as secure memory.
* This configuration assumes 16GB of total DRAM being populated.
*/
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0x0 0x7f000000>,
<0x00000080 0x80000000 0x3 0x80000000>;
numa-node-id = <0>;
};
soc_refclk60mhz: refclk60mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
clock-output-names = "iofpga_clk";
};
soc_hdlcdclk: hdlcdclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <23750000>;
clock-output-names = "hdlcdclk";
};
hdlcd: hdlcd@1c050000 {
compatible = "arm,hdlcd";
reg = <0 0x1c050000 0 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_hdlcdclk>;
clock-names = "pxlclk";
port {
hdlcd0_output: endpoint {
remote-endpoint = <&tda998x_0_input>;
};
};
};
i2c@1c0f0000 {
compatible = "arm,versatile-i2c";
reg = <0x0 0x1c0f0000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
i2c-sda-hold-time-ns = <500>;
clocks = <&soc_refclk60mhz>;
hdmi-transmitter@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
port {
tda998x_0_input: endpoint {
remote-endpoint = <&hdlcd0_output>;
};
};
};
};
};
&pcie_ctlr {
status = "okay";
};
&ccix_pcie_ctlr {
status = "okay";
};
&soc_uart0 {
status = "okay";
};
fdts/n1sdp.dtsi 0 → 100644
View file @ f0b1864f
// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
/*
* Copyright (c) 2019-2020, Arm Limited.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0@0 {
compatible = "arm,neoverse-n1";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
numa-node-id = <0>;
};
cpu1@100 {
compatible = "arm,neoverse-n1";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
numa-node-id = <0>;
};
cpu2@10000 {
compatible = "arm,neoverse-n1";
reg = <0x0 0x10000>;
device_type = "cpu";
enable-method = "psci";
numa-node-id = <0>;
};
cpu3@10100 {
compatible = "arm,neoverse-n1";
reg = <0x0 0x10100>;
device_type = "cpu";
enable-method = "psci";
numa-node-id = <0>;
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
spe-pmu {
compatible = "arm,statistical-profiling-extension-v1";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
soc_refclk100mhz: refclk100mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
soc_uartclk: uartclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "uartclk";
};
soc {
compatible = "arm,neoverse-n1-soc", "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@30000000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#interrupt-cells = <3>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x30000000 0 0x10000>, /* GICD */
<0x0 0x300c0000 0 0x80000>; /* GICR */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
its1: its@30040000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x30040000 0x0 0x20000>;
};
its2: its@30060000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x30060000 0x0 0x20000>;
};
its_ccix: its@30080000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x30080000 0x0 0x20000>;
};
its_pcie: its@300a0000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x300a0000 0x0 0x20000>;
};
};
smmu_ccix: iommu@4f000000 {
compatible = "arm,smmu-v3";
reg = <0 0x4f000000 0 0x40000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "cmdq-sync", "gerror";
msi-parent = <&its1 0>;
#iommu-cells = <1>;
dma-coherent;
};
smmu_pcie: iommu@4f400000 {
compatible = "arm,smmu-v3";
reg = <0 0x4f400000 0 0x40000>;
interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eventq", "cmdq-sync", "gerror";
msi-parent = <&its2 0>;
#iommu-cells = <1>;
dma-coherent;
};
pcie_ctlr: pcie@70000000 {
compatible = "arm,n1sdp-pcie";
device_type = "pci";
reg = <0 0x70000000 0 0x1200000>;
bus-range = <0 17>;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
dma-coherent;
ranges = <0x01000000 0x00 0x00000000 0x00 0x75200000 0x00 0x00010000>,
<0x02000000 0x00 0x71200000 0x00 0x71200000 0x00 0x04000000>,
<0x42000000 0x09 0x00000000 0x09 0x00000000 0x20 0x00000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
msi-map = <0 &its_pcie 0 0x10000>;
iommu-map = <0 &smmu_pcie 0 0x10000>;
status = "disabled";
};
ccix_pcie_ctlr: pcie@68000000 {
compatible = "arm,n1sdp-pcie";
device_type = "pci";
reg = <0 0x68000000 0 0x1200000>;
bus-range = <0 17>;
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
dma-coherent;
ranges = <0x01000000 0x00 0x00000000 0x00 0x6d200000 0x00 0x00010000>,
<0x02000000 0x00 0x69200000 0x00 0x69200000 0x00 0x04000000>,
<0x42000000 0x29 0x00000000 0x29 0x00000000 0x20 0x00000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
msi-map = <0 &its_ccix 0 0x10000>;
iommu-map = <0 &smmu_ccix 0 0x10000>;
status = "disabled";
};
soc_uart0: serial@2a400000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x2a400000 0x0 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
};
};
plat/arm/board/n1sdp/platform.mk
View file @ f0b1864f
...@@ -38,6 +38,8 @@ BL31_SOURCES := ${N1SDP_CPU_SOURCES} \ ...@@ -38,6 +38,8 @@ BL31_SOURCES := ${N1SDP_CPU_SOURCES} \
${N1SDP_BASE}/n1sdp_security.c \ ${N1SDP_BASE}/n1sdp_security.c \
drivers/arm/css/sds/sds.c drivers/arm/css/sds/sds.c
FDT_SOURCES += fdts/${PLAT}-single-chip.dts \
fdts/${PLAT}-multi-chip.dts
# TF-A not required to load the SCP Images # TF-A not required to load the SCP Images
override CSS_LOAD_SCP_IMAGES := 0 override CSS_LOAD_SCP_IMAGES := 0
......
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