Merge pull request #184 from jcastillo-arm/jc/tf-issues/100

FVP: make usage of Trusted DRAM optional at build time

bl1/bl1.ld.S

@@ -35,8 +35,8 @@ OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
 ENTRY(bl1_entrypoint)
 
 MEMORY {
-    ROM (rx): ORIGIN = TZROM_BASE, LENGTH = TZROM_SIZE
-    RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
+    ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT
+    RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT
 }
 
 SECTIONS

bl2/bl2.ld.S

@@ -35,7 +35,7 @@ OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
 ENTRY(bl2_entrypoint)
 
 MEMORY {
-    RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
+    RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT
 }
 
 

bl31/bl31.ld.S

@@ -36,7 +36,7 @@ ENTRY(bl31_entrypoint)
 
 
 MEMORY {
-    RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
+    RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT
 }
 
 

docs/firmware-design.md

@@ -955,22 +955,95 @@ PROGBITS sections then the resulting binary file would contain a bunch of zero
 bytes at the location of this NOBITS section, making the image unnecessarily
 bigger. Smaller images allow faster loading from the FIP to the main memory.
 
-On FVP platforms, we use the Trusted ROM and Trusted SRAM to store the trusted
-firmware binaries.
+On FVP platforms, we use the Trusted ROM, Trusted SRAM and, optionally, Trusted
+DRAM to store the trusted firmware binaries and shared data.
+
+ *    A 4KB page of shared memory is used to store the entrypoint mailboxes
+      and the parameters passed between bootloaders. The shared memory can be
+      allocated either at the top of Trusted SRAM or at the base of Trusted
+      DRAM at build time. When allocated in Trusted SRAM, the amount of Trusted
+      SRAM available to load the bootloader images will be reduced by the size
+      of the shared memory.
 
  *    BL1 is originally sitting in the Trusted ROM at address `0x0`. Its
       read-write data are relocated at the top of the Trusted SRAM at runtime.
+      If the shared memory is allocated in Trusted SRAM, the BL1 read-write data
+      is relocated just below the shared memory.
 
  *    BL3-1 is loaded at the top of the Trusted SRAM, such that its NOBITS
       sections will overwrite BL1 R/W data.
 
  *    BL2 is loaded below BL3-1.
 
- *    The TSP is loaded as the BL3-2 image at the base of the Trusted SRAM. Its
-      NOBITS sections are allowed to overlay BL2.
+ *    The TSP is loaded as the BL3-2 image at the base of either the Trusted
+      SRAM or Trusted DRAM. When loaded into Trusted SRAM, its NOBITS sections
+      are allowed to overlay BL2. When loaded into Trusted DRAM, an offset
+      corresponding to the size of the shared memory is applied to avoid
+      overlap.
 
 This memory layout is designed to give the BL3-2 image as much memory as
-possible. It is illustrated by the following diagram.
+possible when it is loaded into Trusted SRAM. Depending on the location of the
+shared memory page and the TSP, it will result in different memory maps,
+illustrated by the following diagrams.
+
+** Shared data & TSP in Trusted SRAM (default option): **
+
+               Trusted SRAM
+    0x04040000 +----------+
+               |  Shared  |
+    0x0403F000 +----------+  loaded by BL2  ------------------
+               | BL1 (rw) |  <<<<<<<<<<<<<  |  BL3-1 NOBITS  |
+               |----------|  <<<<<<<<<<<<<  |----------------|
+               |          |  <<<<<<<<<<<<<  | BL3-1 PROGBITS |
+               |----------|                 ------------------
+               |   BL2    |  <<<<<<<<<<<<<  |  BL3-2 NOBITS  |
+               |----------|  <<<<<<<<<<<<<  |----------------|
+               |          |  <<<<<<<<<<<<<  | BL3-2 PROGBITS |
+    0x04000000 +----------+                 ------------------
+
+               Trusted ROM
+    0x04000000 +----------+
+               | BL1 (ro) |
+    0x00000000 +----------+
+
+
+** Shared data & TSP in Trusted DRAM: **
+
+               Trusted DRAM
+    0x08000000 +----------+
+               |          |
+               |  BL3-2   |
+               |          |
+    0x06001000 |----------|
+               |  Shared  |
+    0x06000000 +----------+
+
+               Trusted SRAM
+    0x04040000 +----------+  loaded by BL2  ------------------
+               | BL1 (rw) |  <<<<<<<<<<<<<  |  BL3-1 NOBITS  |
+               |----------|  <<<<<<<<<<<<<  |----------------|
+               |          |  <<<<<<<<<<<<<  | BL3-1 PROGBITS |
+               |----------|                 ------------------
+               |   BL2    |
+               |----------|
+               |          |
+    0x04000000 +----------+
+
+               Trusted ROM
+    0x04000000 +----------+
+               | BL1 (ro) |
+    0x00000000 +----------+
+
+** Shared data in Trusted DRAM, TSP in Trusted SRAM: **
+
+               Trusted DRAM
+    0x08000000 +----------+
+               |          |
+               |          |
+               |          |
+    0x06001000 |----------|
+               |  Shared  |
+    0x06000000 +----------+
 
                Trusted SRAM
     0x04040000 +----------+  loaded by BL2  ------------------
@@ -988,8 +1061,8 @@ possible. It is illustrated by the following diagram.
                | BL1 (ro) |
     0x00000000 +----------+
 
-The TSP image may be loaded in Trusted DRAM instead. This doesn't change the
-memory layout of the other boot loader images in Trusted SRAM.
+Loading the TSP image in Trusted DRAM doesn't change the memory layout of the
+other boot loader images in Trusted SRAM.
 
 Each bootloader stage image layout is described by its own linker script. The
 linker scripts export some symbols into the program symbol table. Their values

docs/porting-guide.md

@@ -150,31 +150,6 @@ file is found in [plat/fvp/include/platform_def.h].
     Defines the total number of nodes in the affinity heirarchy at all affinity
     levels used by the platform.
 
-*   **#define : TZROM_BASE**
-
-    Defines the base address of secure ROM on the platform, where the BL1 binary
-    is loaded. This constant is used by the linker scripts to ensure that the
-    BL1 image fits into the available memory.
-
-*   **#define : TZROM_SIZE**
-
-    Defines the size of secure ROM on the platform. This constant is used by the
-    linker scripts to ensure that the BL1 image fits into the available memory.
-
-*   **#define : TZRAM_BASE**
-
-    Defines the base address of the secure RAM on platform, where the data
-    section of the BL1 binary is loaded. The BL2 and BL3-1 images are also
-    loaded in this secure RAM region. This constant is used by the linker
-    scripts to ensure that the BL1 data section and BL2/BL3-1 binary images fit
-    into the available memory.
-
-*   **#define : TZRAM_SIZE**
-
-    Defines the size of the secure RAM on the platform. This constant is used by
-    the linker scripts to ensure that the BL1 data section and BL2/BL3-1 binary
-    images fit into the available memory.
-
 *   **#define : BL1_RO_BASE**
 
     Defines the base address in secure ROM where BL1 originally lives. Must be

docs/user-guide.md

@@ -133,6 +133,8 @@ the build system doesn't track dependency for build options. Therefore, if any
 of the build options are changed from a previous build, a clean build must be
 performed.
 
+#### Common build options
+
 *   `BL30`: Path to BL3-0 image in the host file system. This image is optional.
     If a BL3-0 image is present then this option must be passed for the `fip`
     target
@@ -205,6 +207,19 @@ performed.
     synchronous method) or 1 (BL3-2 is initialized using asynchronous method).
     Default is 0.
 
+#### FVP specific build options
+
+*   `FVP_SHARED_DATA_LOCATION`: location of the shared memory page. Available
+    options:
+      - 'tsram' (default) : top of Trusted SRAM
+      - 'tdram' : base of Trusted DRAM
+
+*   `FVP_TSP_RAM_LOCATION`: location of the TSP binary. Options:
+      - 'tsram' (default) : base of Trusted SRAM
+      - 'tdram' : Trusted DRAM (above shared data)
+
+For a better understanding of FVP options, the FVP memory map is detailed in
+[Firmware Design].
 
 ### Creating a Firmware Image Package
 
@@ -327,11 +342,11 @@ The Firmware Package contains this new image:
 
 On FVP, the TSP binary runs from Trusted SRAM by default. It is also possible
 to run it from Trusted DRAM. This is controlled by the build configuration
-`TSP_RAM_LOCATION`:
+`FVP_TSP_RAM_LOCATION`:
 
     CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- \
     BL33=<path-to>/<bl33_image>                               \
-    make PLAT=fvp SPD=tspd TSP_RAM_LOCATION=tdram all fip
+    make PLAT=fvp SPD=tspd FVP_TSP_RAM_LOCATION=tdram all fip
 
 
 ### Checking source code style

plat/fvp/aarch64/fvp_common.c

@@ -56,9 +56,9 @@ plat_config_t plat_config;
  * configure_mmu_elx() will give the available subset of that,
  */
 const mmap_region_t fvp_mmap[] = {
-	{ TZROM_BASE,	TZROM_BASE,	TZROM_SIZE,
-						MT_MEMORY | MT_RO | MT_SECURE },
-	{ TZDRAM_BASE,	TZDRAM_BASE,	TZDRAM_SIZE,
+	{ FVP_SHARED_RAM_BASE,	FVP_SHARED_RAM_BASE,	FVP_SHARED_RAM_SIZE,
+						MT_MEMORY | MT_RW | MT_SECURE },
+	{ FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_BASE,	FVP_TRUSTED_DRAM_SIZE,
 						MT_MEMORY | MT_RW | MT_SECURE },
 	{ FLASH0_BASE,	FLASH0_BASE,	FLASH0_SIZE,
 						MT_MEMORY | MT_RO | MT_SECURE },

plat/fvp/aarch64/fvp_helpers.S

@@ -34,7 +34,7 @@
 #include <gic_v2.h>
 #include <pl011.h>
 #include "../drivers/pwrc/fvp_pwrc.h"
-#include "../fvp_def.h"
+#include "platform_def.h"
 
 	.globl	platform_get_entrypoint
 	.globl	plat_secondary_cold_boot_setup
@@ -140,7 +140,7 @@ warm_reset:
 	 * its safe to read it here with SO attributes
 	 * ---------------------------------------------
 	 */
-	ldr	x10, =TZDRAM_BASE + MBOX_OFF
+	ldr	x10, =MBOX_BASE
 	bl	platform_get_core_pos
 	lsl	x0, x0, #CACHE_WRITEBACK_SHIFT
 	ldr	x0, [x10, x0]
@@ -153,8 +153,8 @@ _panic:	b	_panic
 	/* -----------------------------------------------------
 	 * void platform_mem_init (void);
 	 *
-	 * Zero out the mailbox registers in the TZDRAM. The
-	 * mmu is turned off right now and only the primary can
+	 * Zero out the mailbox registers in the shared memory.
+	 * The mmu is turned off right now and only the primary can
 	 * ever execute this code. Secondaries will read the
 	 * mailboxes using SO accesses. In short, BL31 will
 	 * update the mailboxes after mapping the tzdram as
@@ -163,7 +163,7 @@ _panic:	b	_panic
 	 * -----------------------------------------------------
 	 */
 func platform_mem_init
-	ldr	x0, =TZDRAM_BASE + MBOX_OFF
+	ldr	x0, =MBOX_BASE
 	mov	w1, #PLATFORM_CORE_COUNT
 loop:
 	str	xzr, [x0], #CACHE_WRITEBACK_GRANULE

plat/fvp/bl1_fvp_setup.c

@@ -76,12 +76,12 @@ void bl1_early_platform_setup(void)
 	console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
 
 	/* Allow BL1 to see the whole Trusted RAM */
-	bl1_tzram_layout.total_base = TZRAM_BASE;
-	bl1_tzram_layout.total_size = TZRAM_SIZE;
+	bl1_tzram_layout.total_base = FVP_TRUSTED_SRAM_BASE;
+	bl1_tzram_layout.total_size = FVP_TRUSTED_SRAM_SIZE;
 
 	/* Calculate how much RAM BL1 is using and how much remains free */
-	bl1_tzram_layout.free_base = TZRAM_BASE;
-	bl1_tzram_layout.free_size = TZRAM_SIZE;
+	bl1_tzram_layout.free_base = FVP_TRUSTED_SRAM_BASE;
+	bl1_tzram_layout.free_size = FVP_TRUSTED_SRAM_SIZE;
 	reserve_mem(&bl1_tzram_layout.free_base,
 		    &bl1_tzram_layout.free_size,
 		    BL1_RAM_BASE,
@@ -114,8 +114,8 @@ void bl1_plat_arch_setup(void)
 
 	fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
 			      bl1_tzram_layout.total_size,
-			      TZROM_BASE,
-			      TZROM_BASE + TZROM_SIZE,
+			      BL1_RO_BASE,
+			      BL1_RO_LIMIT,
 			      BL1_COHERENT_RAM_BASE,
 			      BL1_COHERENT_RAM_LIMIT);
 }

plat/fvp/bl2_fvp_setup.c

@@ -72,6 +72,11 @@ static meminfo_t bl2_tzram_layout
 __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
 		section("tzfw_coherent_mem")));
 
+/* Assert that BL3-1 parameters fit in shared memory */
+CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) <
+	(FVP_SHARED_RAM_BASE + FVP_SHARED_RAM_SIZE),
+	assert_bl31_params_do_not_fit_in_shared_memory);
+
 /*******************************************************************************
  * Reference to structures which holds the arguments which need to be passed
  * to BL31
@@ -97,14 +102,6 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
 {
 	bl2_to_bl31_params_mem_t *bl31_params_mem;
 
-#if TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
-	/*
-	 * Ensure that the secure DRAM memory used for passing BL31 arguments
-	 * does not overlap with the BL32_BASE.
-	 */
-	assert(BL32_BASE > PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t));
-#endif
-
 	/*
 	 * Allocate the memory for all the arguments that needs to
 	 * be passed to BL31

plat/fvp/fvp_def.h

-#/*
+/*
  * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -31,19 +31,29 @@
 #ifndef __FVP_DEF_H__
 #define __FVP_DEF_H__
 
-#include <platform_def.h> /* for TZROM_SIZE */
-
-
 /* Firmware Image Package */
 #define FIP_IMAGE_NAME			"fip.bin"
 #define FVP_PRIMARY_CPU			0x0
 
+/* Memory location options for Shared data and TSP in FVP */
+#define FVP_IN_TRUSTED_SRAM		0
+#define FVP_IN_TRUSTED_DRAM		1
+
 /*******************************************************************************
  * FVP memory map related constants
  ******************************************************************************/
 
+#define FVP_TRUSTED_ROM_BASE	0x00000000
+#define FVP_TRUSTED_ROM_SIZE	0x04000000	/* 64 MB */
+
+#define FVP_TRUSTED_SRAM_BASE	0x04000000
+#define FVP_TRUSTED_SRAM_SIZE	0x00040000	/* 256 KB */
+
+#define FVP_TRUSTED_DRAM_BASE	0x06000000
+#define FVP_TRUSTED_DRAM_SIZE	0x02000000	/* 32 MB */
+
 #define FLASH0_BASE		0x08000000
-#define FLASH0_SIZE		TZROM_SIZE
+#define FLASH0_SIZE		0x04000000
 
 #define FLASH1_BASE		0x0c000000
 #define FLASH1_SIZE		0x04000000
@@ -64,10 +74,27 @@
 #define NSRAM_BASE		0x2e000000
 #define NSRAM_SIZE		0x10000
 
-#define MBOX_OFF		0x1000
-
-/* Base address where parameters to BL31 are stored */
-#define PARAMS_BASE		TZDRAM_BASE
+/* 4KB shared memory */
+#define FVP_SHARED_RAM_SIZE	0x1000
+
+/* Location of shared memory */
+#if (FVP_SHARED_DATA_LOCATION_ID == FVP_IN_TRUSTED_DRAM)
+/* Shared memory at the base of Trusted DRAM */
+# define FVP_SHARED_RAM_BASE		FVP_TRUSTED_DRAM_BASE
+# define FVP_TRUSTED_SRAM_LIMIT		(FVP_TRUSTED_SRAM_BASE \
+					+ FVP_TRUSTED_SRAM_SIZE)
+#elif (FVP_SHARED_DATA_LOCATION_ID == FVP_IN_TRUSTED_SRAM)
+# if (FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM)
+#  error "Shared data in Trusted SRAM and TSP in Trusted DRAM is not supported"
+# endif
+/* Shared memory at the top of the Trusted SRAM */
+# define FVP_SHARED_RAM_BASE		(FVP_TRUSTED_SRAM_BASE \
+					+ FVP_TRUSTED_SRAM_SIZE \
+					- FVP_SHARED_RAM_SIZE)
+# define FVP_TRUSTED_SRAM_LIMIT		FVP_SHARED_RAM_BASE
+#else
+# error "Unsupported FVP_SHARED_DATA_LOCATION_ID value"
+#endif
 
 #define DRAM1_BASE		0x80000000ull
 #define DRAM1_SIZE		0x80000000ull
@@ -229,5 +256,15 @@
 #define FVP_NSAID_HDLCD0		2
 #define FVP_NSAID_CLCD			7
 
+/*******************************************************************************
+ *  Shared Data
+ ******************************************************************************/
+
+/* Entrypoint mailboxes */
+#define MBOX_BASE		FVP_SHARED_RAM_BASE
+#define MBOX_SIZE		0x200
+
+/* Base address where parameters to BL31 are stored */
+#define PARAMS_BASE		(MBOX_BASE + MBOX_SIZE)
 
 #endif /* __FVP_DEF_H__ */

plat/fvp/fvp_pm.c

@@ -103,7 +103,7 @@ int fvp_affinst_on(unsigned long mpidr,
 	} while (psysr & PSYSR_AFF_L0);
 
 	linear_id = platform_get_core_pos(mpidr);
-	fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
+	fvp_mboxes = (mailbox_t *)MBOX_BASE;
 	fvp_mboxes[linear_id].value = sec_entrypoint;
 	flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
 			   sizeof(unsigned long));
@@ -240,7 +240,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
 
 			/* Program the jump address for the target cpu */
 			linear_id = platform_get_core_pos(mpidr);
-			fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
+			fvp_mboxes = (mailbox_t *)MBOX_BASE;
 			fvp_mboxes[linear_id].value = sec_entrypoint;
 			flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
 					   sizeof(unsigned long));
@@ -329,7 +329,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
 		fvp_pwrc_clr_wen(mpidr);
 
 		/* Zero the jump address in the mailbox for this cpu */
-		fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
+		fvp_mboxes = (mailbox_t *)MBOX_BASE;
 		linear_id = platform_get_core_pos(mpidr);
 		fvp_mboxes[linear_id].value = 0;
 		flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],

plat/fvp/include/platform_def.h

@@ -32,6 +32,7 @@
 #define __PLATFORM_DEF_H__
 
 #include <arch.h>
+#include <../fvp_def.h>
 
 
 /*******************************************************************************
@@ -83,32 +84,21 @@
 #define MAX_IO_DEVICES			3
 #define MAX_IO_HANDLES			4
 
-/*******************************************************************************
- * Platform memory map related constants
- ******************************************************************************/
-#define TZROM_BASE		0x00000000
-#define TZROM_SIZE		0x04000000
-
-#define TZRAM_BASE		0x04000000
-#define TZRAM_SIZE		0x40000
-
-/* Location of trusted dram on the base fvp */
-#define TZDRAM_BASE		0x06000000
-#define TZDRAM_SIZE		0x02000000
-
 /*******************************************************************************
  * BL1 specific defines.
  * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
  * addresses.
  ******************************************************************************/
-#define BL1_RO_BASE			TZROM_BASE
-#define BL1_RO_LIMIT			(TZROM_BASE + TZROM_SIZE)
+#define BL1_RO_BASE			FVP_TRUSTED_ROM_BASE
+#define BL1_RO_LIMIT			(FVP_TRUSTED_ROM_BASE \
+					+ FVP_TRUSTED_ROM_SIZE)
 /*
- * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
- * the current BL1 RW debug size plus a little space for growth.
+ * Put BL1 RW at the top of the Trusted SRAM (just below the shared memory, if
+ * present). BL1_RW_BASE is calculated using the current BL1 RW debug size plus
+ * a little space for growth.
  */
-#define BL1_RW_BASE			(TZRAM_BASE + TZRAM_SIZE - 0x6000)
-#define BL1_RW_LIMIT			(TZRAM_BASE + TZRAM_SIZE)
+#define BL1_RW_BASE			(FVP_TRUSTED_SRAM_LIMIT - 0x6000)
+#define BL1_RW_LIMIT			FVP_TRUSTED_SRAM_LIMIT
 
 /*******************************************************************************
  * BL2 specific defines.
@@ -124,12 +114,13 @@
  * BL31 specific defines.
  ******************************************************************************/
 /*
- * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
- * current BL3-1 debug size plus a little space for growth.
+ * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
+ * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
+ * little space for growth.
  */
-#define BL31_BASE			(TZRAM_BASE + TZRAM_SIZE - 0x1D000)
+#define BL31_BASE			(FVP_TRUSTED_SRAM_LIMIT - 0x1D000)
 #define BL31_PROGBITS_LIMIT		BL1_RW_BASE
-#define BL31_LIMIT			(TZRAM_BASE + TZRAM_SIZE)
+#define BL31_LIMIT			FVP_TRUSTED_SRAM_LIMIT
 
 /*******************************************************************************
  * BL32 specific defines.
@@ -137,22 +128,20 @@
 /*
  * On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
  */
-#define TSP_IN_TZRAM			0
-#define TSP_IN_TZDRAM			1
-
-#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
-# define TSP_SEC_MEM_BASE		TZRAM_BASE
-# define TSP_SEC_MEM_SIZE		TZRAM_SIZE
-# define BL32_BASE			TZRAM_BASE
+#if FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_SRAM
+# define TSP_SEC_MEM_BASE		FVP_TRUSTED_SRAM_BASE
+# define TSP_SEC_MEM_SIZE		FVP_TRUSTED_SRAM_SIZE
+# define BL32_BASE			FVP_TRUSTED_SRAM_BASE
 # define BL32_PROGBITS_LIMIT		BL2_BASE
 # define BL32_LIMIT			BL31_BASE
-#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
-# define TSP_SEC_MEM_BASE		TZDRAM_BASE
-# define TSP_SEC_MEM_SIZE		TZDRAM_SIZE
-# define BL32_BASE			(TZDRAM_BASE + 0x2000)
-# define BL32_LIMIT			(TZDRAM_BASE + (1 << 21))
+#elif FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM
+# define TSP_SEC_MEM_BASE		FVP_TRUSTED_DRAM_BASE
+# define TSP_SEC_MEM_SIZE		FVP_TRUSTED_DRAM_SIZE
+# define BL32_BASE			(FVP_TRUSTED_DRAM_BASE \
+					+ FVP_SHARED_RAM_SIZE)
+# define BL32_LIMIT			(FVP_TRUSTED_DRAM_BASE + (1 << 21))
 #else
-# error "Unsupported TSP_RAM_LOCATION_ID value"
+# error "Unsupported FVP_TSP_RAM_LOCATION_ID value"
 #endif
 
 /*******************************************************************************

plat/fvp/platform.mk

@@ -28,20 +28,37 @@
 # POSSIBILITY OF SUCH DAMAGE.
 #
 
+# Shared memory may be allocated at the top of Trusted SRAM (tsram) or at the
+# base of Trusted SRAM (tdram)
+FVP_SHARED_DATA_LOCATION	:=	tsram
+ifeq (${FVP_SHARED_DATA_LOCATION}, tsram)
+  FVP_SHARED_DATA_LOCATION_ID := FVP_IN_TRUSTED_SRAM
+else ifeq (${FVP_SHARED_DATA_LOCATION}, tdram)
+  FVP_SHARED_DATA_LOCATION_ID := FVP_IN_TRUSTED_DRAM
+else
+  $(error "Unsupported FVP_SHARED_DATA_LOCATION value")
+endif
+
 # On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
 # Trusted SRAM is the default.
-TSP_RAM_LOCATION	:=	tsram
-
-ifeq (${TSP_RAM_LOCATION}, tsram)
-  TSP_RAM_LOCATION_ID := TSP_IN_TZRAM
-else ifeq (${TSP_RAM_LOCATION}, tdram)
-  TSP_RAM_LOCATION_ID := TSP_IN_TZDRAM
+FVP_TSP_RAM_LOCATION	:=	tsram
+ifeq (${FVP_TSP_RAM_LOCATION}, tsram)
+  FVP_TSP_RAM_LOCATION_ID := FVP_IN_TRUSTED_SRAM
+else ifeq (${FVP_TSP_RAM_LOCATION}, tdram)
+  FVP_TSP_RAM_LOCATION_ID := FVP_IN_TRUSTED_DRAM
 else
-  $(error "Unsupported TSP_RAM_LOCATION value")
+  $(error "Unsupported FVP_TSP_RAM_LOCATION value")
+endif
+
+ifeq (${FVP_SHARED_DATA_LOCATION}, tsram)
+  ifeq (${FVP_TSP_RAM_LOCATION}, tdram)
+    $(error Shared data in Trusted SRAM and TSP in Trusted DRAM is not supported)
+  endif
 endif
 
-# Process TSP_RAM_LOCATION_ID flag
-$(eval $(call add_define,TSP_RAM_LOCATION_ID))
+# Process flags
+$(eval $(call add_define,FVP_SHARED_DATA_LOCATION_ID))
+$(eval $(call add_define,FVP_TSP_RAM_LOCATION_ID))
 
 PLAT_INCLUDES		:=	-Iplat/fvp/include/