Skip to content
GitLab
Menu
Projects
Groups
Snippets
Help
Projects
Groups
Snippets
Loading...
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Sign in / Register
Toggle navigation
Menu
Open sidebar
adam.huang
Arm Trusted Firmware
Commits
f1a1653c
Commit
f1a1653c
authored
4 years ago
by
Manish Pandey
Committed by
TrustedFirmware Code Review
4 years ago
Browse files
Options
Download
Plain Diff
Merge "Fix exception in save/restore of EL2 registers." into integration
parents
611efd96
30ee3755
Changes
2
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
include/lib/el3_runtime/aarch64/context.h
+59
-60
include/lib/el3_runtime/aarch64/context.h
lib/el3_runtime/aarch64/context.S
+65
-69
lib/el3_runtime/aarch64/context.S
with
124 additions
and
129 deletions
+124
-129
include/lib/el3_runtime/aarch64/context.h
View file @
f1a1653c
...
...
@@ -168,76 +168,75 @@
#define CTX_ELR_EL2 U(0x58)
#define CTX_ESR_EL2 U(0x60)
#define CTX_FAR_EL2 U(0x68)
#define CTX_FPEXC32_EL2 U(0x70)
#define CTX_HACR_EL2 U(0x78)
#define CTX_HCR_EL2 U(0x80)
#define CTX_HPFAR_EL2 U(0x88)
#define CTX_HSTR_EL2 U(0x90)
#define CTX_ICC_SRE_EL2 U(0x98)
#define CTX_ICH_HCR_EL2 U(0xa0)
#define CTX_ICH_VMCR_EL2 U(0xa8)
#define CTX_MAIR_EL2 U(0xb0)
#define CTX_MDCR_EL2 U(0xb8)
#define CTX_PMSCR_EL2 U(0xc0)
#define CTX_SCTLR_EL2 U(0xc8)
#define CTX_SPSR_EL2 U(0xd0)
#define CTX_SP_EL2 U(0xd8)
#define CTX_TCR_EL2 U(0xe0)
#define CTX_TPIDR_EL2 U(0xe8)
#define CTX_TTBR0_EL2 U(0xf0)
#define CTX_VBAR_EL2 U(0xf8)
#define CTX_VMPIDR_EL2 U(0x100)
#define CTX_VPIDR_EL2 U(0x108)
#define CTX_VTCR_EL2 U(0x110)
#define CTX_VTTBR_EL2 U(0x118)
#define CTX_HACR_EL2 U(0x70)
#define CTX_HCR_EL2 U(0x78)
#define CTX_HPFAR_EL2 U(0x80)
#define CTX_HSTR_EL2 U(0x88)
#define CTX_ICC_SRE_EL2 U(0x90)
#define CTX_ICH_HCR_EL2 U(0x98)
#define CTX_ICH_VMCR_EL2 U(0xa0)
#define CTX_MAIR_EL2 U(0xa8)
#define CTX_MDCR_EL2 U(0xb0)
#define CTX_PMSCR_EL2 U(0xb8)
#define CTX_SCTLR_EL2 U(0xc0)
#define CTX_SPSR_EL2 U(0xc8)
#define CTX_SP_EL2 U(0xd0)
#define CTX_TCR_EL2 U(0xd8)
#define CTX_TPIDR_EL2 U(0xe0)
#define CTX_TTBR0_EL2 U(0xe8)
#define CTX_VBAR_EL2 U(0xf0)
#define CTX_VMPIDR_EL2 U(0xf8)
#define CTX_VPIDR_EL2 U(0x100)
#define CTX_VTCR_EL2 U(0x108)
#define CTX_VTTBR_EL2 U(0x110)
// Only if MTE registers in use
#define CTX_TFSR_EL2 U(0x1
20
)
#define CTX_TFSR_EL2 U(0x1
18
)
// Only if ENABLE_MPAM_FOR_LOWER_ELS==1
#define CTX_MPAM2_EL2 U(0x12
8
)
#define CTX_MPAMHCR_EL2 U(0x1
30
)
#define CTX_MPAMVPM0_EL2 U(0x13
8
)
#define CTX_MPAMVPM1_EL2 U(0x1
40
)
#define CTX_MPAMVPM2_EL2 U(0x14
8
)
#define CTX_MPAMVPM3_EL2 U(0x1
50
)
#define CTX_MPAMVPM4_EL2 U(0x15
8
)
#define CTX_MPAMVPM5_EL2 U(0x1
60
)
#define CTX_MPAMVPM6_EL2 U(0x16
8
)
#define CTX_MPAMVPM7_EL2 U(0x1
70
)
#define CTX_MPAMVPMV_EL2 U(0x17
8
)
#define CTX_MPAM2_EL2 U(0x12
0
)
#define CTX_MPAMHCR_EL2 U(0x1
28
)
#define CTX_MPAMVPM0_EL2 U(0x13
0
)
#define CTX_MPAMVPM1_EL2 U(0x1
38
)
#define CTX_MPAMVPM2_EL2 U(0x14
0
)
#define CTX_MPAMVPM3_EL2 U(0x1
48
)
#define CTX_MPAMVPM4_EL2 U(0x15
0
)
#define CTX_MPAMVPM5_EL2 U(0x1
58
)
#define CTX_MPAMVPM6_EL2 U(0x16
0
)
#define CTX_MPAMVPM7_EL2 U(0x1
68
)
#define CTX_MPAMVPMV_EL2 U(0x17
0
)
// Starting with Armv8.6
#define CTX_HAFGRTR_EL2 U(0x18
0
)
#define CTX_HDFGRTR_EL2 U(0x18
8
)
#define CTX_HDFGWTR_EL2 U(0x1
90
)
#define CTX_HFGITR_EL2 U(0x19
8
)
#define CTX_HFGRTR_EL2 U(0x1
a0
)
#define CTX_HFGWTR_EL2 U(0x1a
8
)
#define CTX_CNTPOFF_EL2 U(0x1
b0
)
#define CTX_HAFGRTR_EL2 U(0x1
7
8)
#define CTX_HDFGRTR_EL2 U(0x18
0
)
#define CTX_HDFGWTR_EL2 U(0x1
88
)
#define CTX_HFGITR_EL2 U(0x19
0
)
#define CTX_HFGRTR_EL2 U(0x1
98
)
#define CTX_HFGWTR_EL2 U(0x1a
0
)
#define CTX_CNTPOFF_EL2 U(0x1
a8
)
// Starting with Armv8.4
#define CTX_CNTHPS_CTL_EL2 U(0x1b
8
)
#define CTX_CNTHPS_CVAL_EL2 U(0x1
c0
)
#define CTX_CNTHPS_TVAL_EL2 U(0x1c
8
)
#define CTX_CNTHVS_CTL_EL2 U(0x1
d0
)
#define CTX_CNTHVS_CVAL_EL2 U(0x1d
8
)
#define CTX_CNTHVS_TVAL_EL2 U(0x1
e0
)
#define CTX_CNTHV_CTL_EL2 U(0x1e
8
)
#define CTX_CNTHV_CVAL_EL2 U(0x1
f0
)
#define CTX_CNTHV_TVAL_EL2 U(0x1f
8
)
#define CTX_CONTEXTIDR_EL2 U(0x
200
)
#define CTX_SDER32_EL2 U(0x20
8
)
#define CTX_TTBR1_EL2 U(0x2
1
0)
#define CTX_VDISR_EL2 U(0x21
8
)
#define CTX_VNCR_EL2 U(0x2
20
)
#define CTX_VSESR_EL2 U(0x22
8
)
#define CTX_VSTCR_EL2 U(0x2
30
)
#define CTX_VSTTBR_EL2 U(0x23
8
)
#define CTX_TRFCR_EL2 U(0x2
40
)
#define CTX_CNTHPS_CTL_EL2 U(0x1b
0
)
#define CTX_CNTHPS_CVAL_EL2 U(0x1
b8
)
#define CTX_CNTHPS_TVAL_EL2 U(0x1c
0
)
#define CTX_CNTHVS_CTL_EL2 U(0x1
c8
)
#define CTX_CNTHVS_CVAL_EL2 U(0x1d
0
)
#define CTX_CNTHVS_TVAL_EL2 U(0x1
d8
)
#define CTX_CNTHV_CTL_EL2 U(0x1e
0
)
#define CTX_CNTHV_CVAL_EL2 U(0x1
e8
)
#define CTX_CNTHV_TVAL_EL2 U(0x1f
0
)
#define CTX_CONTEXTIDR_EL2 U(0x
1f8
)
#define CTX_SDER32_EL2 U(0x20
0
)
#define CTX_TTBR1_EL2 U(0x20
8
)
#define CTX_VDISR_EL2 U(0x21
0
)
#define CTX_VNCR_EL2 U(0x2
18
)
#define CTX_VSESR_EL2 U(0x22
0
)
#define CTX_VSTCR_EL2 U(0x2
28
)
#define CTX_VSTTBR_EL2 U(0x23
0
)
#define CTX_TRFCR_EL2 U(0x2
38
)
// Starting with Armv8.5
#define CTX_SCXTNUM_EL2 U(0x24
8
)
#define CTX_SCXTNUM_EL2 U(0x24
0
)
/* Align to the next 16 byte boundary */
#define CTX_EL2_SYSREGS_END U(0x250)
...
...
This diff is collapsed.
Click to expand it.
lib/el3_runtime/aarch64/context.S
View file @
f1a1653c
...
...
@@ -71,53 +71,52 @@ func el2_sysregs_context_save
mrs
x15
,
far_el2
stp
x14
,
x15
,
[
x0
,
#
CTX_ESR_EL2
]
mrs
x16
,
fpexc32
_el2
mrs
x17
,
h
a
cr_el2
stp
x16
,
x17
,
[
x0
,
#
CTX_
FPEXC32
_EL2
]
mrs
x16
,
hacr
_el2
mrs
x17
,
hcr_el2
stp
x16
,
x17
,
[
x0
,
#
CTX_
HACR
_EL2
]
mrs
x9
,
h
c
r_el2
mrs
x10
,
h
pfa
r_el2
stp
x9
,
x10
,
[
x0
,
#
CTX_H
C
R_EL2
]
mrs
x9
,
h
pfa
r_el2
mrs
x10
,
h
st
r_el2
stp
x9
,
x10
,
[
x0
,
#
CTX_H
PFA
R_EL2
]
mrs
x11
,
hstr_el
2
mrs
x12
,
IC
C_SRE
_EL2
stp
x11
,
x12
,
[
x0
,
#
CTX_
HSTR
_EL2
]
mrs
x11
,
ICC_SRE_EL
2
mrs
x12
,
IC
H_HCR
_EL2
stp
x11
,
x12
,
[
x0
,
#
CTX_
ICC_SRE
_EL2
]
mrs
x13
,
ICH_
H
CR_EL2
mrs
x14
,
ICH_VMCR_EL
2
stp
x13
,
x14
,
[
x0
,
#
CTX_ICH_
H
CR_EL2
]
mrs
x13
,
ICH_
VM
CR_EL2
mrs
x14
,
mair_el
2
stp
x13
,
x14
,
[
x0
,
#
CTX_ICH_
VM
CR_EL2
]
mrs
x15
,
m
ai
r_el2
mrs
x16
,
mdcr_el
2
stp
x15
,
x16
,
[
x0
,
#
CTX_M
AI
R_EL2
]
mrs
x15
,
m
dc
r_el2
mrs
x16
,
PMSCR_EL
2
stp
x15
,
x16
,
[
x0
,
#
CTX_M
DC
R_EL2
]
mrs
x17
,
PMSCR_EL
2
mrs
x9
,
s
ctl
r_el2
stp
x17
,
x9
,
[
x0
,
#
CTX_
PM
SCR_EL2
]
mrs
x17
,
sctlr_el
2
mrs
x9
,
s
ps
r_el2
stp
x17
,
x9
,
[
x0
,
#
CTX_SC
TL
R_EL2
]
mrs
x10
,
sp
sr
_el2
mrs
x11
,
sp
_el2
stp
x10
,
x11
,
[
x0
,
#
CTX_SP
SR
_EL2
]
mrs
x10
,
sp_el2
mrs
x11
,
tcr
_el2
stp
x10
,
x11
,
[
x0
,
#
CTX_SP_EL2
]
mrs
x12
,
t
c
r_el2
mrs
x13
,
t
pidr
_el2
stp
x12
,
x13
,
[
x0
,
#
CTX_T
C
R_EL2
]
mrs
x12
,
t
pid
r_el2
mrs
x13
,
t
tbr0
_el2
stp
x12
,
x13
,
[
x0
,
#
CTX_T
PID
R_EL2
]
mrs
x14
,
ttbr0
_el2
mrs
x15
,
v
ba
r_el2
stp
x14
,
x15
,
[
x0
,
#
CTX_
TTBR0
_EL2
]
mrs
x14
,
vbar
_el2
mrs
x15
,
v
mpid
r_el2
stp
x14
,
x15
,
[
x0
,
#
CTX_
VBAR
_EL2
]
mrs
x16
,
v
m
pidr_el2
mrs
x17
,
v
pid
r_el2
stp
x16
,
x17
,
[
x0
,
#
CTX_V
M
PIDR_EL2
]
mrs
x16
,
vpidr_el2
mrs
x17
,
v
tc
r_el2
stp
x16
,
x17
,
[
x0
,
#
CTX_VPIDR_EL2
]
mrs
x9
,
vtcr_el2
mrs
x10
,
vttbr_el2
stp
x9
,
x10
,
[
x0
,
#
CTX_VTCR_EL2
]
mrs
x9
,
vttbr_el2
str
x9
,
[
x0
,
#
CTX_VTTBR_EL2
]
#if CTX_INCLUDE_MTE_REGS
mrs
x1
1
,
TFSR_EL2
str
x1
1
,
[
x0
,
#
CTX_TFSR_EL2
]
mrs
x1
0
,
TFSR_EL2
str
x1
0
,
[
x0
,
#
CTX_TFSR_EL2
]
#endif
#if ENABLE_MPAM_FOR_LOWER_ELS
...
...
@@ -277,51 +276,48 @@ func el2_sysregs_context_restore
msr
esr_el2
,
x14
msr
far_el2
,
x15
ldp
x16
,
x17
,
[
x0
,
#
CTX_FPEXC32_EL2
]
msr
fpexc32_el2
,
x16
msr
hacr_el2
,
x17
ldp
x9
,
x10
,
[
x0
,
#
CTX_HCR_EL2
]
msr
hcr_el2
,
x9
msr
hpfar_el2
,
x10
ldp
x16
,
x17
,
[
x0
,
#
CTX_HACR_EL2
]
msr
hacr_el2
,
x16
msr
hcr_el2
,
x17
ldp
x
11
,
x1
2
,
[
x0
,
#
CTX_H
ST
R_EL2
]
msr
h
st
r_el2
,
x
11
msr
ICC_SRE_EL
2
,
x1
2
ldp
x
9
,
x1
0
,
[
x0
,
#
CTX_H
PFA
R_EL2
]
msr
h
pfa
r_el2
,
x
9
msr
hstr_el
2
,
x1
0
ldp
x1
3
,
x1
4
,
[
x0
,
#
CTX_IC
H_HCR
_EL2
]
msr
IC
H_HCR
_EL2
,
x1
3
msr
ICH_
VM
CR_EL2
,
x1
4
ldp
x1
1
,
x1
2
,
[
x0
,
#
CTX_IC
C_SRE
_EL2
]
msr
IC
C_SRE
_EL2
,
x1
1
msr
ICH_
H
CR_EL2
,
x1
2
ldp
x1
5
,
x1
6
,
[
x0
,
#
CTX_
MAI
R_EL2
]
msr
mair_el
2
,
x1
5
msr
m
dc
r_el2
,
x1
6
ldp
x1
3
,
x1
4
,
[
x0
,
#
CTX_
ICH_VMC
R_EL2
]
msr
ICH_VMCR_EL
2
,
x1
3
msr
m
ai
r_el2
,
x1
4
ldr
x17
,
[
x0
,
#
CTX_PMSCR_EL2
]
msr
PMSCR_EL2
,
x17
ldp
x15
,
x16
,
[
x0
,
#
CTX_MDCR_EL2
]
msr
mdcr_el2
,
x15
msr
PMSCR_EL2
,
x16
ldp
x1
0
,
x
11
,
[
x0
,
#
CTX_SPSR_EL2
]
msr
spsr_el2
,
x1
0
msr
sp_el2
,
x
11
ldp
x1
7
,
x
9
,
[
x0
,
#
CTX_SPSR_EL2
]
msr
spsr_el2
,
x1
7
msr
sp_el2
,
x
9
ldr
x12
,
[
x0
,
#
CTX_TPIDR_EL2
]
msr
tpidr_el2
,
x12
ldp
x10
,
x11
,
[
x0
,
#
CTX_TPIDR_EL2
]
msr
tpidr_el2
,
x10
msr
ttbr0_el2
,
x11
ldp
x1
4
,
x1
5
,
[
x0
,
#
CTX_
TTBR0
_EL2
]
msr
ttbr0
_el2
,
x1
4
msr
v
ba
r_el2
,
x1
5
ldp
x1
2
,
x1
3
,
[
x0
,
#
CTX_
VBAR
_EL2
]
msr
vbar
_el2
,
x1
2
msr
v
mpid
r_el2
,
x1
3
ldp
x1
6
,
x1
7
,
[
x0
,
#
CTX_V
M
PIDR_EL2
]
msr
v
m
pidr_el2
,
x1
6
msr
v
pid
r_el2
,
x1
7
ldp
x1
4
,
x1
5
,
[
x0
,
#
CTX_VPIDR_EL2
]
msr
vpidr_el2
,
x1
4
msr
v
tc
r_el2
,
x1
5
ldp
x9
,
x10
,
[
x0
,
#
CTX_VTCR_EL2
]
msr
vtcr_el2
,
x9
msr
vttbr_el2
,
x10
ldr
x16
,
[
x0
,
#
CTX_VTTBR_EL2
]
msr
vttbr_el2
,
x16
#if CTX_INCLUDE_MTE_REGS
ldr
x1
1
,
[
x0
,
#
CTX_TFSR_EL2
]
msr
TFSR_EL2
,
x1
1
ldr
x1
7
,
[
x0
,
#
CTX_TFSR_EL2
]
msr
TFSR_EL2
,
x1
7
#endif
#if ENABLE_MPAM_FOR_LOWER_ELS
...
...
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment
Menu
Projects
Groups
Snippets
Help