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adam.huang
Arm Trusted Firmware
Commits
f1f8ea20
Commit
f1f8ea20
authored
5 years ago
by
Alexei Fedorov
Committed by
TrustedFirmware Code Review
5 years ago
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Merge "allwinner: Move the NOBITS region to SRAM A1" into integration
parents
743600b2
ed306a86
master
v2.5
v2.5-rc1
v2.5-rc0
v2.4
v2.4-rc2
v2.4-rc1
v2.4-rc0
v2.3
v2.3-rc2
v2.3-rc1
v2.3-rc0
arm_cca_v0.2
arm_cca_v0.1
No related merge requests found
Changes
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2 changed files
plat/allwinner/common/allwinner-common.mk
+3
-0
plat/allwinner/common/allwinner-common.mk
plat/allwinner/common/include/platform_def.h
+5
-1
plat/allwinner/common/include/platform_def.h
with
8 additions
and
1 deletion
+8
-1
plat/allwinner/common/allwinner-common.mk
View file @
f1f8ea20
...
@@ -55,6 +55,9 @@ PROGRAMMABLE_RESET_ADDRESS := 1
...
@@ -55,6 +55,9 @@ PROGRAMMABLE_RESET_ADDRESS := 1
# Allow mapping read-only data as execute-never.
# Allow mapping read-only data as execute-never.
SEPARATE_CODE_AND_RODATA
:=
1
SEPARATE_CODE_AND_RODATA
:=
1
# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
SEPARATE_NOBITS_REGION
:=
1
# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
RESET_TO_BL31
:=
1
RESET_TO_BL31
:=
1
...
...
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plat/allwinner/common/include/platform_def.h
View file @
f1f8ea20
/*
/*
* Copyright (c) 2017-201
8
, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-201
9
, ARM Limited and Contributors. All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
* SPDX-License-Identifier: BSD-3-Clause
*/
*/
...
@@ -16,6 +16,10 @@
...
@@ -16,6 +16,10 @@
#define BL31_BASE SUNXI_SRAM_A2_BASE
#define BL31_BASE SUNXI_SRAM_A2_BASE
#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE)
#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE)
/* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */
#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000)
#define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE)
/* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */
/* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */
#define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20))
#define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20))
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