Commit f1f8ea20 authored by Alexei Fedorov's avatar Alexei Fedorov Committed by TrustedFirmware Code Review
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Merge "allwinner: Move the NOBITS region to SRAM A1" into integration

parents 743600b2 ed306a86
...@@ -55,6 +55,9 @@ PROGRAMMABLE_RESET_ADDRESS := 1 ...@@ -55,6 +55,9 @@ PROGRAMMABLE_RESET_ADDRESS := 1
# Allow mapping read-only data as execute-never. # Allow mapping read-only data as execute-never.
SEPARATE_CODE_AND_RODATA := 1 SEPARATE_CODE_AND_RODATA := 1
# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
SEPARATE_NOBITS_REGION := 1
# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL # BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
RESET_TO_BL31 := 1 RESET_TO_BL31 := 1
......
/* /*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -16,6 +16,10 @@ ...@@ -16,6 +16,10 @@
#define BL31_BASE SUNXI_SRAM_A2_BASE #define BL31_BASE SUNXI_SRAM_A2_BASE
#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE) #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE)
/* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */
#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000)
#define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE)
/* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */ /* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */
#define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20)) #define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20))
......
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