Merge pull request #1759 from vwadekar/armlink-support

Armlink support

bl31/bl31.ld.S

@@ -224,9 +224,11 @@ SECTIONS
          */
         . = ALIGN(CACHE_WRITEBACK_GRANULE);
         __BAKERY_LOCK_START__ = .;
+        __PERCPU_BAKERY_LOCK_START__ = .;
         *(bakery_lock)
         . = ALIGN(CACHE_WRITEBACK_GRANULE);
-        __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
+        __PERCPU_BAKERY_LOCK_END__ = .;
+        __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__);
         . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
         __BAKERY_LOCK_END__ = .;
 

bl32/sp_min/sp_min.ld.S

@@ -151,9 +151,11 @@ SECTIONS
          */
         . = ALIGN(CACHE_WRITEBACK_GRANULE);
         __BAKERY_LOCK_START__ = .;
+        __PERCPU_BAKERY_LOCK_START__ = .;
         *(bakery_lock)
         . = ALIGN(CACHE_WRITEBACK_GRANULE);
-        __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
+        __PERCPU_BAKERY_LOCK_END__ = .;
+        __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__);
         . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
         __BAKERY_LOCK_END__ = .;
 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE

lib/aarch64/armclang_printf.S

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,7 +13,13 @@
 	.globl __2printf
 
 func __0printf
-__1printf:
-__2printf:
-        b	printf
+	b	printf
 endfunc __0printf
+
+func __1printf
+	b	printf
+endfunc __1printf
+
+func __2printf
+	b	printf
+endfunc __2printf

lib/aarch64/misc_helpers.S

 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,6 +7,7 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <assert_macros.S>
+#include <common/bl_common.h>
 #include <lib/xlat_tables/xlat_tables_defs.h>
 
 #if !ERROR_DEPRECATED
@@ -18,16 +19,13 @@
 
 	.globl	zero_normalmem
 	.globl	zeromem
-	.globl	zeromem16
 	.globl	memcpy16
 
 	.globl	disable_mmu_el1
 	.globl	disable_mmu_el3
 	.globl	disable_mmu_icache_el1
 	.globl	disable_mmu_icache_el3
-
 	.globl	fixup_gdt_reloc
-
 #if SUPPORT_VFP
 	.globl	enable_vfp
 #endif

lib/locks/bakery/bakery_lock_normal.c

@@ -51,7 +51,9 @@ CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \
  * Use the linker defined symbol which has evaluated the size reqiurement.
  * This is not as efficient as using a platform defined constant
  */
-IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_SIZE__, PERCPU_BAKERY_LOCK_SIZE);
+IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_START__, BAKERY_LOCK_START);
+IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_END__, BAKERY_LOCK_END);
+#define PERCPU_BAKERY_LOCK_SIZE (BAKERY_LOCK_END - BAKERY_LOCK_START)
 #endif
 
 static inline bakery_lock_t *get_bakery_info(unsigned int cpu_ix,

lib/xlat_tables_v2/xlat_tables_core.c

@@ -21,7 +21,7 @@
 #include "xlat_tables_private.h"
 
 /* Helper function that cleans the data cache only if it is enabled. */
-static inline void xlat_clean_dcache_range(uintptr_t addr, size_t size)
+static inline __attribute__((unused)) void xlat_clean_dcache_range(uintptr_t addr, size_t size)
 {
 	if (is_dcache_enabled())
 		clean_dcache_range(addr, size);

plat/common/aarch64/platform_helpers.S

 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -26,8 +26,6 @@
 	.weak	plat_handle_double_fault
 	.weak	plat_handle_el3_ea
 
-	.globl	platform_get_core_pos
-
 #define MPIDR_RES_BIT_MASK	0xff000000
 
 	/* -----------------------------------------------------

plat/common/aarch64/platform_mp_stack.S

 /*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,8 +12,6 @@
 	.local	platform_normal_stacks
 	.weak	plat_get_my_stack
 	.weak	plat_set_my_stack
-	.globl	platform_get_stack
-	.globl	platform_set_stack
 
 	/* ---------------------------------------------------------------------
 	 * When the compatility layer is disabled, the new platform APIs

plat/common/aarch64/platform_up_stack.S

 /*
- * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,8 +12,6 @@
 	.local	platform_normal_stacks
 	.weak	plat_set_my_stack
 	.weak	plat_get_my_stack
-	.weak	platform_set_stack
-	.weak	platform_get_stack
 
 	/* -----------------------------------------------------
 	 * uintptr_t plat_get_my_stack ()

plat/mediatek/mt6795/bl31.ld.S

@@ -113,9 +113,11 @@ SECTIONS
          */
         . = ALIGN(CACHE_WRITEBACK_GRANULE);
         __BAKERY_LOCK_START__ = .;
+        __PERCPU_BAKERY_LOCK_START__ = .;
         *(bakery_lock)
         . = ALIGN(CACHE_WRITEBACK_GRANULE);
-        __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
+        __PERCPU_BAKERY_LOCK_END__ = .;
+        __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__);
         . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
         __BAKERY_LOCK_END__ = .;
 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE

plat/nvidia/tegra/include/platform_def.h

@@ -9,10 +9,15 @@
 
 #include <arch.h>
 #include <lib/utils_def.h>
-#include <plat/common/common_def.h>
 
 #include <tegra_def.h>
 
+/*
+ * Platform binary types for linking
+ */
+#define PLATFORM_LINKER_FORMAT		"elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH		aarch64
+
 /*******************************************************************************
  * Generic platform constants
  ******************************************************************************/
@@ -59,6 +64,6 @@
  * integrated and external caches.
  ******************************************************************************/
 #define CACHE_WRITEBACK_SHIFT		6
-#define CACHE_WRITEBACK_GRANULE		(U(1) << CACHE_WRITEBACK_SHIFT)
+#define CACHE_WRITEBACK_GRANULE		(0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */
 
 #endif /* PLATFORM_DEF_H */

plat/nvidia/tegra/soc/t186/plat_psci_handlers.c

@@ -283,7 +283,7 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta
 		val = params_from_bl2->tzdram_base +
 			tegra186_get_cpu_reset_handler_size();
 		memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
-			 (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE);
+			 (uintptr_t)BL31_END - (uintptr_t)BL31_BASE);
 	}
 
 	return PSCI_E_SUCCESS;

plat/nvidia/tegra/soc/t186/plat_trampoline.S

 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <arch.h>
 #include <asm_macros.S>
+#include <common/bl_common.h>
 #include <memctrl_v2.h>
 #include <plat/common/common_def.h>
 #include <tegra_def.h>