Merge changes from topic "add-versal-soc-support" into integration

* changes:
  plat: xilinx: Move pm_client.h to common directory
  plat: xilinx: versal: Make silicon default build target
  xilinx: versal: Wire silicon default setup
  versal: Increase OCM memory size for DEBUG builds
  plat: xilinx: versal: Dont set IOU switch clock
  arm64: versal: Adjust cpu clock for versal virtual
  xilinx: versal: Add support for PM_GET_OPERATING_CHARACTERISTIC EEMI call
  plat: versal: Add Get_ChipID API
  plat: xilinx: versal: Add load Pdi API support
  xilinx: versal: Add feature check API
  xilinx: versal: Implement set wakeup source for client
  plat: xilinx: versal: Add GET_CALLBACK_DATA function
  xilinx: versal: Add PSCI APIs for system shutdown & reset
  xilinx: versal: Add PSCI APIs for suspend/resume
  xilinx: versal: Remove no_pmc ops to ON power domain
  xilinx: versal: Add set wakeup source API
  xilinx: versal: Add client wakeup API
  xilinx: versal: Add query data API
  xilinx: versal: Add request wakeup API
  xilinx: versal: Add PM_INIT_FINALIZE API for versal
  xilinx: versal: Add support of PM_GET_TRUSTZONE_VERSION API
  xilinx: versal: enable ipi mailbox service
  xilinx: move ipi mailbox svc to xilinx common
  plat: xilinx: versal: Implement PM IOCTL API
  xilinx: versal: Implement power down/restart related EEMI API
  xilinx: versal: Add SMC handler for EEMI API
  xilinx: versal: Implement PLL related PM APIs
  xilinx: versal: Implement clock related PM APIs
  xilinx: versal: Implement pin control related PM APIs
  xilinx: versal: Implement reset related PM APIs
  xilinx: versal: Implement device related PM APIs
  xilinx: versal: Add support for suspend related APIs
  xilinx: versal: Add get_api_version support
  xilinx: Add support to send PM API to PMC using IPI for versal
  plat: xilinx: versal: Move versal_def.h to include directory
  plat: xilinx: versal: Move versal_private.h to include directory
  plat: xilinx: zynqmp: Use GIC framework for warm restart

plat/xilinx/versal/pm_service/pm_svc_main.h

+/*
+ * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PM_SVC_MAIN_H
+#define PM_SVC_MAIN_H
+
+#include <pm_common.h>
+
+int pm_setup(void);
+uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3,
+			uint64_t x4, void *cookie, void *handle,
+			uint64_t flags);
+
+#endif /* PM_SVC_MAIN_H */

plat/xilinx/versal/sip_svc_setup.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,6 +10,9 @@
 #include <common/runtime_svc.h>
 #include <tools_share/uuid.h>
 
+#include "ipi_mailbox_svc.h"
+#include "pm_svc_main.h"
+
 /* SMC function IDs for SiP Service queries */
 #define VERSAL_SIP_SVC_CALL_COUNT	0x8200ff00
 #define VERSAL_SIP_SVC_UID		0x8200ff01
@@ -22,7 +25,9 @@
 /* These macros are used to identify PM calls from the SMC function ID */
 #define PM_FID_MASK	0xf000u
 #define PM_FID_VALUE	0u
+#define IPI_FID_VALUE	0x1000u
 #define is_pm_fid(_fid) (((_fid) & PM_FID_MASK) == PM_FID_VALUE)
+#define is_ipi_fid(_fid) (((_fid) & PM_FID_MASK) == IPI_FID_VALUE)
 
 /* SiP Service UUID */
 DEFINE_SVC_UUID2(versal_sip_uuid,
@@ -36,6 +41,9 @@ DEFINE_SVC_UUID2(versal_sip_uuid,
  */
 static int32_t sip_svc_setup(void)
 {
+	/* PM implementation as SiP Service */
+	pm_setup();
+
 	return 0;
 }
 
@@ -54,6 +62,18 @@ uintptr_t sip_svc_smc_handler(uint32_t smc_fid,
 			     void *handle,
 			     u_register_t flags)
 {
+	/* Let PM SMC handler deal with PM-related requests */
+	if (is_pm_fid(smc_fid)) {
+		return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
+				      flags);
+	}
+
+	/* Let IPI SMC handler deal with IPI-related requests */
+	if (is_ipi_fid(smc_fid)) {
+		return ipi_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
+				      flags);
+	}
+
 	/* Let PM SMC handler deal with PM-related requests */
 	switch (smc_fid) {
 	case VERSAL_SIP_SVC_CALL_COUNT:

plat/xilinx/versal/versal_gicv3.c

 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <plat_private.h>
 #include <platform_def.h>
 
 #include <common/interrupt_props.h>
@@ -11,8 +12,6 @@
 #include <lib/utils.h>
 #include <plat/common/platform.h>
 
-#include "versal_private.h"
-
 /******************************************************************************
  * The following functions are defined as weak to allow a platform to override
  * the way the GICv3 driver is initialised and used.

plat/xilinx/versal/versal_ipi.c

+/*
+ * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * Versal IPI agent registers access management
+ */
+
+#include <errno.h>
+#include <ipi.h>
+#include <plat_ipi.h>
+#include <plat_private.h>
+#include <string.h>
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <lib/bakery_lock.h>
+#include <lib/mmio.h>
+
+/* versal ipi configuration table */
+const static struct ipi_config versal_ipi_table[] = {
+	/* A72 IPI */
+	[IPI_ID_APU] = {
+		.ipi_bit_mask = IPI0_TRIG_BIT,
+		.ipi_reg_base = IPI0_REG_BASE,
+		.secure_only = 0,
+	},
+
+	/* PMC IPI */
+	[IPI_ID_PMC] = {
+		.ipi_bit_mask = PMC_IPI_TRIG_BIT,
+		.ipi_reg_base = IPI0_REG_BASE,
+		.secure_only = 0,
+	},
+
+	/* RPU0 IPI */
+	[IPI_ID_RPU0] = {
+		.ipi_bit_mask = IPI1_TRIG_BIT,
+		.ipi_reg_base = IPI1_REG_BASE,
+		.secure_only = 0,
+	},
+
+	/* RPU1 IPI */
+	[IPI_ID_RPU1] = {
+		.ipi_bit_mask = IPI2_TRIG_BIT,
+		.ipi_reg_base = IPI2_REG_BASE,
+		.secure_only = 0,
+	},
+
+	/* IPI3 IPI */
+	[IPI_ID_3] = {
+		.ipi_bit_mask = IPI3_TRIG_BIT,
+		.ipi_reg_base = IPI3_REG_BASE,
+		.secure_only = 0,
+	},
+
+	/* IPI4 IPI */
+	[IPI_ID_4] = {
+		.ipi_bit_mask = IPI4_TRIG_BIT,
+		.ipi_reg_base = IPI4_REG_BASE,
+		.secure_only = 0,
+	},
+
+	/* IPI5 IPI */
+	[IPI_ID_5] = {
+		.ipi_bit_mask = IPI5_TRIG_BIT,
+		.ipi_reg_base = IPI5_REG_BASE,
+		.secure_only = 0,
+	},
+};
+
+/* versal_ipi_config_table_init() - Initialize versal IPI configuration data
+ *
+ * @ipi_config_table  - IPI configuration table
+ * @ipi_total - Total number of IPI available
+ *
+ */
+void versal_ipi_config_table_init(void)
+{
+	ipi_config_table_init(versal_ipi_table, ARRAY_SIZE(versal_ipi_table));
+}

plat/xilinx/zynqmp/plat_psci.c

 /*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -100,9 +100,8 @@ static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state)
 	for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
 		VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
 			__func__, i, target_state->pwr_domain_state[i]);
-
+	plat_arm_gic_pcpu_init();
 	gicv2_cpuif_enable();
-	gicv2_pcpu_distif_init();
 }
 
 static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state)

plat/xilinx/zynqmp/platform.mk

@@ -11,6 +11,8 @@ SEPARATE_CODE_AND_RODATA := 1
 ZYNQMP_WDT_RESTART := 0
 ZYNQMP_IPI_CRC_CHECK := 0
 override RESET_TO_BL31 := 1
+override GICV2_G0_FOR_EL3 := 1
+override WARMBOOT_ENABLE_DCACHE_EARLY := 1
 
 # Do not enable SVE
 ENABLE_SVE_FOR_NS	:= 0
@@ -53,9 +55,9 @@ endif
 PLAT_INCLUDES		:=	-Iinclude/plat/arm/common/			\
 				-Iinclude/plat/arm/common/aarch64/		\
 				-Iplat/xilinx/common/include/			\
+				-Iplat/xilinx/common/ipi_mailbox_service/	\
 				-Iplat/xilinx/zynqmp/include/			\
 				-Iplat/xilinx/zynqmp/pm_service/		\
-				-Iplat/xilinx/zynqmp/ipi_mailbox_service/
 
 PLAT_BL_COMMON_SOURCES	:=	lib/xlat_tables/xlat_tables_common.c		\
 				lib/xlat_tables/aarch64/xlat_tables.c		\
@@ -78,6 +80,7 @@ BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
 				lib/cpus/aarch64/aem_generic.S			\
 				lib/cpus/aarch64/cortex_a53.S			\
 				plat/common/plat_psci_common.c			\
+				plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
 				plat/xilinx/common/pm_service/pm_ipi.c		\
 				plat/xilinx/zynqmp/bl31_zynqmp_setup.c		\
 				plat/xilinx/zynqmp/plat_psci.c			\
@@ -90,5 +93,8 @@ BL31_SOURCES		+=	drivers/arm/cci/cci.c				\
 				plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c	\
 				plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c	\
 				plat/xilinx/zynqmp/pm_service/pm_api_clock.c	\
-				plat/xilinx/zynqmp/pm_service/pm_client.c	\
-				plat/xilinx/zynqmp/ipi_mailbox_service/ipi_mailbox_svc.c
+				plat/xilinx/zynqmp/pm_service/pm_client.c
+
+ifneq (${RESET_TO_BL31},1)
+  $(error "Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1.")
+endif

plat/xilinx/zynqmp/pm_service/pm_svc_main.c

@@ -77,8 +77,12 @@ static void trigger_wdt_restart(void)
 
 	INFO("Active Cores: %d\n", active_cores);
 
-	/* trigger SGI to active cores */
-	gicv2_raise_sgi(ARM_IRQ_SEC_SGI_7, target_cpu_list);
+	for (i = PLATFORM_CORE_COUNT - 1; i >= 0; i--) {
+		if (target_cpu_list & (1 << i)) {
+			/* trigger SGI to active cores */
+			plat_ic_raise_el3_sgi(ARM_IRQ_SEC_SGI_7, i);
+		}
+	}
 }
 
 /**
@@ -106,6 +110,8 @@ static uint64_t ttc_fiq_handler(uint32_t id, uint32_t flags, void *handle,
 {
 	INFO("BL31: Got TTC FIQ\n");
 
+	plat_ic_end_of_interrupt(id);
+
 	/* Clear TTC interrupt by reading interrupt register */
 	mmio_read_32(TTC3_INTR_REGISTER_1);