Skip to content

GitLab

Commit f4d1312c authored by davidcunado-arm's avatar davidcunado-arm Committed by GitHub
Browse files

Merge pull request #739 from rockchip-linux/fixes-latency 

rockchip: fix A72 L2CTLR_DATA_RAM_LATENCY to 5
parents 4f0b2e81 4ea8dc4e
master v2.5 v2.5-rc1 v2.5-rc0 v2.4 v2.4-rc2 v2.4-rc1 v2.4-rc0 v2.3 v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.2 v2.2-rc2 v2.2-rc1 v2.2-rc0 v2.1 v2.1-rc1 v2.1-rc0 v2.0 v2.0-rc0 v1.6 v1.6-rc1 v1.6-rc0 v1.5 v1.5-rc3 v1.5-rc2 v1.5-rc1 v1.5-rc0 v1.4 v1.4-rc0 arm_cca_v0.2 arm_cca_v0.1
No related merge requests found
Hide whitespace changes
Inline Side-by-side
Showing
with 1 addition and 1 deletion
+1 -1
plat/rockchip/common/aarch64/plat_helpers.S
View file @ f4d1312c
......@@ -67,7 +67,7 @@ handler_a72:
* Set the L2 Data RAM latency for Cortex-A72.
* Set the L2 Tag RAM latency to for Cortex-A72.
*/
mov x0, #((2 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
mov x0, #((5 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
(0x1 << 5))
msr L2CTLR_EL1, x0
isb
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment