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Commit f63e9f4c authored by Manish Pandey's avatar Manish Pandey Committed by TrustedFirmware Code Review
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Merge "fdts: a5ds: add L2 cache node in devicetree" into integration

parents 98ee29c6 79c6c342
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fdts/a5ds.dts
View file @ f63e9f4c
...@@ -27,24 +27,28 @@ ...@@ -27,24 +27,28 @@
compatible = "arm,cortex-a5"; compatible = "arm,cortex-a5";
enable-method = "psci"; enable-method = "psci";
reg = <0>; reg = <0>;
next-level-cache = <&L2>;
}; };
cpu@1 { cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a5"; compatible = "arm,cortex-a5";
enable-method = "psci"; enable-method = "psci";
reg = <1>; reg = <1>;
next-level-cache = <&L2>;
}; };
cpu@2 { cpu@2 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a5"; compatible = "arm,cortex-a5";
enable-method = "psci"; enable-method = "psci";
reg = <2>; reg = <2>;
next-level-cache = <&L2>;
}; };
cpu@3 { cpu@3 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a5"; compatible = "arm,cortex-a5";
enable-method = "psci"; enable-method = "psci";
reg = <3>; reg = <3>;
next-level-cache = <&L2>;
}; };
}; };
...@@ -53,6 +57,16 @@ ...@@ -53,6 +57,16 @@
reg = <0x80000000 0x7F000000>; reg = <0x80000000 0x7F000000>;
}; };
L2: cache-controller@1C010000 {
compatible = "arm,pl310-cache";
reg = <0x1C010000 0x1000>;
interrupts = <0 84 4>;
cache-level = <2>;
cache-unified;
arm,data-latency = <1 1 1>;
arm,tag-latency = <1 1 1>;
};
refclk100mhz: refclk100mhz { refclk100mhz: refclk100mhz {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
......
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