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adam.huang
Arm Trusted Firmware
Commits
f7694165
Commit
f7694165
authored
Jul 17, 2019
by
Soby Mathew
Committed by
TrustedFirmware Code Review
Jul 17, 2019
Browse files
Merge "rcar_gen3: drivers: ddr: Replace BITn with BIT(n) macro" into integration
parents
d0d0f171
8ddd91b0
Changes
8
Hide whitespace changes
Inline
Side-by-side
drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h
View file @
f7694165
/*
* Copyright (c) 2015-201
7
, Renesas Electronics Corporation
* Copyright (c) 2015-201
9
, Renesas Electronics Corporation
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
...
...
@@ -18,9 +18,6 @@
extern
"C"
{
#endif
/* __cplusplus */
#define BIT0 0x00000001U
#define BIT30 0x40000000U
/* DBSC registers */
#define DBSC_D3_DBSYSCONF1 0xE6790004U
...
...
drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h
View file @
f7694165
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2018
-2019
, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
...
...
@@ -11,10 +11,6 @@
extern
"C"
{
#endif
/* __cplusplus */
#define BIT0 0x00000001U
#define BIT11 0x00000800U
#define BIT30 0x40000000U
/* DBSC registers */
#define DBSC_E3_DBSYSCONF1 0xE6790004U
...
...
drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h
View file @
f7694165
/*
* Copyright (c) 2015-201
6
, Renesas Electronics Corporation
* Copyright (c) 2015-201
9
, Renesas Electronics Corporation
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
...
...
@@ -12,9 +12,6 @@
extern
"C"
{
#endif
/* __cplusplus */
#define BIT0 0x00000001U
#define BIT30 0x40000000U
/* DBSC registers */
// modified , last 2016.12.08
...
...
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
View file @
f7694165
/*
* Copyright (c) 2015-201
7
, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-201
9
, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
...
...
@@ -73,7 +73,7 @@ static void init_ddr_d3_1866(void)
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x80010000
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000008
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x000B8000
);
...
...
@@ -92,19 +92,19 @@ static void init_ddr_d3_1866(void)
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x00010073
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000090
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0C058A00
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000090
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x04058A00
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000003
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0780C700
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000007
);
while
(
(
BIT30
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
30
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000004
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0A206F89
);
...
...
@@ -131,7 +131,7 @@ static void init_ddr_d3_1866(void)
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x0000001A
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x33C03C10
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x000000A7
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0D0D0D0D
);
...
...
@@ -167,12 +167,12 @@ static void init_ddr_d3_1866(void)
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x00010181
);
WriteReg_32
(
DBSC_D3_DBCMD
,
0x08000001
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x00010601
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
for
(
uint32_t
i
=
0
;
i
<
2
;
i
++
)
{
...
...
@@ -216,14 +216,14 @@ static void init_ddr_d3_1866(void)
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x00010801
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000005
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0xC1AA00D8
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0001F001
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x000000AF
);
RegVal_R2
=
ReadReg_32
(
DBSC_D3_DBPDRGD0
);
...
...
@@ -241,7 +241,7 @@ static void init_ddr_d3_1866(void)
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x00010401
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
for
(
uint32_t
i
=
0
;
i
<
2
;
i
++
)
{
...
...
@@ -286,12 +286,12 @@ static void init_ddr_d3_1866(void)
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x00015001
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000003
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0380C700
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000007
);
while
(
(
BIT30
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
!=
0
);
while
(
(
BIT
(
30
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
!=
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000021
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0024643E
);
...
...
@@ -388,7 +388,7 @@ static void init_ddr_d3_1600(void)
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x80010000
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000008
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x000B8000
);
...
...
@@ -407,19 +407,19 @@ static void init_ddr_d3_1600(void)
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x00010073
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000090
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0C058900
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000090
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x04058900
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000003
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0780C700
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000007
);
while
(
(
BIT30
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
30
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000004
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x08C05FF0
);
...
...
@@ -446,7 +446,7 @@ static void init_ddr_d3_1600(void)
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x0000001A
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x33C03C10
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x000000A7
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0D0D0D0D
);
...
...
@@ -482,12 +482,12 @@ static void init_ddr_d3_1600(void)
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x00010181
);
WriteReg_32
(
DBSC_D3_DBCMD
,
0x08000001
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x00010601
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
for
(
uint32_t
i
=
0
;
i
<
2
;
i
++
)
{
...
...
@@ -531,14 +531,14 @@ static void init_ddr_d3_1600(void)
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x00010801
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000005
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0xC1AA00D8
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0001F001
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x000000AF
);
RegVal_R2
=
ReadReg_32
(
DBSC_D3_DBPDRGD0
);
...
...
@@ -556,7 +556,7 @@ static void init_ddr_d3_1600(void)
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x00010401
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
for
(
uint32_t
i
=
0
;
i
<
2
;
i
++
)
{
...
...
@@ -600,12 +600,12 @@ static void init_ddr_d3_1600(void)
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x00015001
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000003
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0380C700
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000007
);
while
(
(
BIT30
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
!=
0
);
while
(
(
BIT
(
30
)
&
ReadReg_32
(
DBSC_D3_DBPDRGD0
))
!=
0
);
WriteReg_32
(
DBSC_D3_DBPDRGA0
,
0x00000021
);
WriteReg_32
(
DBSC_D3_DBPDRGD0
,
0x0024643E
);
...
...
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
View file @
f7694165
...
...
@@ -75,7 +75,7 @@ uint32_t init_ddr(void)
}
/* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
ddr_md
=
(
ReadReg_32
(
RST_MODEMR
)
>>
19
)
&
BIT
0
;
ddr_md
=
(
ReadReg_32
(
RST_MODEMR
)
>>
19
)
&
BIT
(
0
)
;
/* 1584Mbps setting */
if
(
ddr_md
==
0
)
{
...
...
@@ -86,7 +86,7 @@ uint32_t init_ddr(void)
WriteReg_32
(
CPG_SRCR4
,
0x20000000
);
WriteReg_32
(
0xE61500DC
,
0xe2200000
);
/* Change to 1584Mbps */
while
((
BIT11
&
ReadReg_32
(
CPG_PLLECR
))
==
0
);
while
((
BIT
(
11
)
&
ReadReg_32
(
CPG_PLLECR
))
==
0
);
WriteReg_32
(
CPG_SRSTCLR4
,
0x20000000
);
...
...
@@ -203,7 +203,7 @@ uint32_t init_ddr(void)
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x80010000
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
/* rev.0.03 add Comment */
/****************************************************************************
...
...
@@ -240,7 +240,7 @@ uint32_t init_ddr(void)
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00010073
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
/* rev.0.03 add Comment */
/****************************************************************************
...
...
@@ -265,7 +265,7 @@ uint32_t init_ddr(void)
}
/* ddr_md */
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000003
);
if
(
byp_ctl
==
1
)
{
...
...
@@ -274,7 +274,7 @@ uint32_t init_ddr(void)
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x0780C700
);
}
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000007
);
while
((
BIT30
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
30
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000004
);
...
...
@@ -358,7 +358,7 @@ uint32_t init_ddr(void)
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x0000001A
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x33C03C10
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x000000A7
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x0D0D0D0D
);
...
...
@@ -389,7 +389,7 @@ uint32_t init_ddr(void)
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00010181
);
WriteReg_32
(
DBSC_E3_DBCMD
,
0x08840001
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
/* rev.0.03 add Comment */
/****************************************************************************
...
...
@@ -398,7 +398,7 @@ uint32_t init_ddr(void)
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00010601
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
for
(
i
=
0
;
i
<
4
;
i
++
)
{
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x000000B1
+
i
*
0x20
);
...
...
@@ -462,7 +462,7 @@ uint32_t init_ddr(void)
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00010801
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
/****************************************************************************
* Initial_Step5(Read Data Bit Deskew)
...
...
@@ -474,7 +474,7 @@ uint32_t init_ddr(void)
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00011001
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
if
(
pdqsr_ctl
==
1
)
{
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x000000A0
);
...
...
@@ -505,7 +505,7 @@ if (pdqsr_ctl == 1) {
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00012001
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
/****************************************************************************
* Initial_Step7(Read Data Eye Training)
...
...
@@ -536,7 +536,7 @@ if (pdqsr_ctl == 1) {
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00014001
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
if
(
pdqsr_ctl
==
1
)
{
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x000000A0
);
...
...
@@ -567,7 +567,7 @@ if (pdqsr_ctl == 1) {
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00018001
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
/* rev.0.03 add Comment */
/****************************************************************************
...
...
@@ -586,7 +586,7 @@ if (pdqsr_ctl == 1) {
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00010401
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
for
(
i
=
0
;
i
<
4
;
i
++
)
{
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x000000B1
+
i
*
0x20
);
...
...
@@ -648,7 +648,7 @@ if (pdqsr_ctl == 1) {
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00015001
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
/* rev.0.08 */
if
(
lcdl_ctl
==
1
)
{
...
...
@@ -732,7 +732,7 @@ if (pdqsr_ctl == 1) {
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x0380C700
);
}
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000007
);
while
((
BIT30
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
!=
0
);
while
((
BIT
(
30
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
!=
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000021
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x0024643E
);
...
...
@@ -865,7 +865,7 @@ uint32_t recovery_from_backup_mode(void)
}
/* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
ddr_md
=
(
ReadReg_32
(
RST_MODEMR
)
>>
19
)
&
BIT
0
;
ddr_md
=
(
ReadReg_32
(
RST_MODEMR
)
>>
19
)
&
BIT
(
0
)
;
/* 1584Mbps setting */
if
(
ddr_md
==
0
)
{
...
...
@@ -876,7 +876,7 @@ uint32_t recovery_from_backup_mode(void)
WriteReg_32
(
CPG_SRCR4
,
0x20000000
);
WriteReg_32
(
0xE61500DC
,
0xe2200000
);
/* Change to 1584Mbps */
while
((
BIT11
&
ReadReg_32
(
CPG_PLLECR
))
==
0
);
while
((
BIT
(
11
)
&
ReadReg_32
(
CPG_PLLECR
))
==
0
);
WriteReg_32
(
CPG_SRSTCLR4
,
0x20000000
);
...
...
@@ -1001,7 +1001,7 @@ uint32_t recovery_from_backup_mode(void)
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x0000001A
);
/* DDR_ACIOCR0 */
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x33C03C10
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000007
);
while
((
BIT30
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
30
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000004
);
...
...
@@ -1089,13 +1089,13 @@ uint32_t recovery_from_backup_mode(void)
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000021
);
/* DDR_DSGCR */
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x0024641E
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
/* DDR_PGSR0 */
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
/* DDR_PIR */
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x40010000
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
/* DDR_PGSR0 */
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000092
);
/* DDR_ZQ0DR */
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0xC2C59AB5
);
...
...
@@ -1125,7 +1125,7 @@ uint32_t recovery_from_backup_mode(void)
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00050001
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
/* DDR_PGSR0 */
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
/* ddr backupmode end */
if
(
ddrBackup
)
{
...
...
@@ -1153,19 +1153,19 @@ uint32_t recovery_from_backup_mode(void)
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00000003
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
/* DDR_PGSR0 */
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
/* DDR_PIR */
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x80010000
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
/* DDR_PGSR0 */
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
/* DDR_PIR */
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00010073
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
/* DDR_PGSR0 */
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000090
);
/* DDR_ZQCR */
...
...
@@ -1193,7 +1193,7 @@ uint32_t recovery_from_backup_mode(void)
* recovery_Step2(PHY setting 2)
***************************************************************************/
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x000000A7
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x0D0D0D0D
);
...
...
@@ -1233,21 +1233,21 @@ uint32_t recovery_from_backup_mode(void)
WriteReg_32
(
DBSC_E3_DBRFCNF2
,
0x00010000
);
WriteReg_32
(
DBSC_E3_DBRFEN
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBCMD
,
0x0A840001
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBWAIT
))
!=
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBWAIT
))
!=
0
);
WriteReg_32
(
DBSC_E3_DBCMD
,
0x00000000
);
WriteReg_32
(
DBSC_E3_DBCMD
,
0x04840010
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBWAIT
))
!=
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBWAIT
))
!=
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
/* DDR_PGSR0 */
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
/* DDR_PIR */
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00010701
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
/* DDR_PGSR0 */
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
for
(
i
=
0
;
i
<
4
;
i
++
)
{
...
...
@@ -1309,7 +1309,7 @@ uint32_t recovery_from_backup_mode(void)
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00010801
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000005
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0xC1AA00D8
);
...
...
@@ -1318,7 +1318,7 @@ uint32_t recovery_from_backup_mode(void)
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00011001
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
if
(
pdqsr_ctl
==
1
)
{
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x000000A0
);
...
...
@@ -1346,7 +1346,7 @@ if (pdqsr_ctl == 1) {
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00012001
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
if
(
pdqsr_ctl
==
1
)
{
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x000000A0
);
...
...
@@ -1374,7 +1374,7 @@ if (pdqsr_ctl == 1) {
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00014001
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
if
(
pdqsr_ctl
==
1
)
{
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x000000A0
);
...
...
@@ -1402,7 +1402,7 @@ if (pdqsr_ctl == 1) {
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00018001
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x000000A0
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x7C000285
);
...
...
@@ -1417,7 +1417,7 @@ if (pdqsr_ctl == 1) {
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00010401
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
for
(
i
=
0
;
i
<
4
;
i
++
)
{
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x000000B1
+
i
*
0x20
);
...
...
@@ -1476,7 +1476,7 @@ if (pdqsr_ctl == 1) {
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000001
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x00015001
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000006
);
while
((
BIT
0
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
while
((
BIT
(
0
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
==
0
);
/* rev.0.08 */
if
(
lcdl_ctl
==
1
)
{
...
...
@@ -1561,7 +1561,7 @@ if (pdqsr_ctl == 1) {
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x0380C700
);
}
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000007
);
while
((
BIT30
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
!=
0
);
while
((
BIT
(
30
)
&
ReadReg_32
(
DBSC_E3_DBPDRGD0
))
!=
0
);
WriteReg_32
(
DBSC_E3_DBPDRGA0
,
0x00000021
);
WriteReg_32
(
DBSC_E3_DBPDRGD0
,
0x0024643E
);
...
...
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
View file @
f7694165
/*
* Copyright (c) 2015-201
6
, Renesas Electronics Corporation
* Copyright (c) 2015-201
9
, Renesas Electronics Corporation
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/utils_def.h>
#include <stdint.h>
#include "boot_init_dram.h"
#include "boot_init_dram_regdef_v3m.h"
...
...
@@ -98,7 +99,7 @@ static uint32_t init_ddr_v3m_1600(void)
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000001
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X80010000
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000008
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X000B8000
);
...
...
@@ -117,19 +118,19 @@ static uint32_t init_ddr_v3m_1600(void)
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000001
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X00010073
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000090
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X0C058900
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000090
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X04058900
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000003
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X0780C700
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000007
);
while
(
(
BIT30
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
30
)
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000004
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X08C0C170
);
...
...
@@ -156,7 +157,7 @@ static uint32_t init_ddr_v3m_1600(void)
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X0000001A
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X13C03C10
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X000000A7
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X0D0D0D0D
);
...
...
@@ -186,12 +187,12 @@ static uint32_t init_ddr_v3m_1600(void)
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X00010181
);
WriteReg_32
(
DBSC_V3M_DBCMD
,
0x08000001
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000001
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X00010601
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
for
(
uint32_t
i
=
0
;
i
<
4
;
i
++
)
{
...
...
@@ -238,14 +239,14 @@ static uint32_t init_ddr_v3m_1600(void)
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000001
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X00010801
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000005
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0XC1AA00B8
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000001
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X0001F001
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X000000A0
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X7C000285
);
...
...
@@ -260,7 +261,7 @@ static uint32_t init_ddr_v3m_1600(void)
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000001
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X00010401
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
for
(
uint32_t
i
=
0
;
i
<
4
;
i
++
)
{
...
...
@@ -309,12 +310,12 @@ static uint32_t init_ddr_v3m_1600(void)
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000001
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X00015001
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000006
);
while
(
(
BIT
0
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
while
(
(
BIT
(
0
)
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
==
0
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000003
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X0380C700
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000007
);
while
(
(
BIT30
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
!=
0
);
while
(
(
BIT
(
30
)
&
ReadReg_32
(
DBSC_V3M_DBPDRGD0
))
!=
0
);
WriteReg_32
(
DBSC_V3M_DBPDRGA0
,
0X00000021
);
WriteReg_32
(
DBSC_V3M_DBPDRGD0
,
0X0024643E
);
...
...
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
View file @
f7694165
...
...
@@ -4221,10 +4221,10 @@ int32_t rcar_dram_init(void)
Thermal sensor setting
***********************************************************************/
dataL
=
mmio_read_32
(
CPG_MSTPSR5
);
if
(
dataL
&
BIT22
)
{
/* case THS/TSC Standby */
dataL
&=
~
(
BIT22
);
if
(
dataL
&
BIT
(
22
)
)
{
/* case THS/TSC Standby */
dataL
&=
~
(
BIT
(
22
)
)
;
cpg_write_32
(
CPG_SMSTPCR5
,
dataL
);
while
((
BIT22
)
&
mmio_read_32
(
CPG_MSTPSR5
));
/* wait bit=0 */
while
((
BIT
(
22
)
)
&
mmio_read_32
(
CPG_MSTPSR5
));
/* wait bit=0 */
}
/* THCTR Bit6: PONM=0 , Bit0: THSST=0 */
...
...
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
View file @
f7694165
...
...
@@ -1623,12 +1623,7 @@ static const uint32_t TermcodeBySample[20][3] = {
#define PFC_PUD6 0xE6060458U
#define GPIO_INDT5 0xE605500CU
#define GPIO_INDT6 0xE605540CU
#define BIT25 BIT(25)
#define BIT22 BIT(22)
#define BIT15 BIT(15)
#define BIT0 BIT(0)
#define GPIO_GPSR6 (0xE6060118U)
#define GPIO_GPSR6 0xE6060118U
#if (RCAR_GEN3_ULCB == 0)
static
void
pfc_write_and_poll
(
uint32_t
a
,
uint32_t
v
)
...
...
@@ -1659,17 +1654,17 @@ static uint32_t opencheck_SSI_WS6(void)
pud5_bak
=
mmio_read_32
(
PFC_PUD5
);
dsb_sev
();
dataL
=
(
gpsr6_bak
&
~
BIT15
);
dataL
=
(
gpsr6_bak
&
~
BIT
(
15
)
)
;
pfc_write_and_poll
(
GPIO_GPSR6
,
dataL
);
/* Pull-Up/Down Enable (PUEN5[22]=1) */
dataL
=
puen5_bak
;
dataL
|=
(
BIT22
);
dataL
|=
(
BIT
(
22
)
)
;
pfc_write_and_poll
(
PFC_PUEN5
,
dataL
);
/* Pull-Down-Enable (PUD5[22]=0, PUEN5[22]=1) */
dataL
=
pud5_bak
;
dataL
&=
~
(
BIT22
);
dataL
&=
~
(
BIT
(
22
)
)
;
pfc_write_and_poll
(
PFC_PUD5
,
dataL
);
/* GPSR6[15]=SSI_WS6 */
rcar_micro_delay
(
10
);
...
...
@@ -1678,7 +1673,7 @@ static uint32_t opencheck_SSI_WS6(void)
/* Pull-Up-Enable (PUD5[22]=1, PUEN5[22]=1) */
dataL
=
pud5_bak
;
dataL
|=
(
BIT22
);
dataL
|=
(
BIT
(
22
)
)
;
pfc_write_and_poll
(
PFC_PUD5
,
dataL
);
/* GPSR6[15]=SSI_WS6 */
...
...
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