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Commit f85ab341 authored by Madhukar Pappireddy's avatar Madhukar Pappireddy Committed by TrustedFirmware Code Review
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Merge changes I4451ca03,I29be60ec,Ia30bd332,I72fe2275,I37bd65b0 into integration 

* changes:
  feat(plat/nxp/lx2): add SUPPORTED_BOOT_MODE definition
  feat(plat/nxp/common): add build macro for BOOT_MODE validation checking
  refactor(plat/nxp/common): moved soc make-variables to new soc_common_def.mk
  refactor(plat/nxp/lx216x): clean up platform configure file
  refactor(plat/nxp/common): moved plat make-variables to new plat_common_def.mk
parents 2a008779 28b3221a
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plat/nxp/common/plat_make_helper/plat_common_def.mk 0 → 100644
View file @ f85ab341
# Copyright 2020-2021 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Include build macros, for example: SET_NXP_MAKE_FLAG
include plat/nxp/common/plat_make_helper/plat_build_macros.mk
# Adding platform specific defines
$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
ifeq (${POVDD_ENABLE},yes)
$(eval $(call add_define,CONFIG_POVDD_ENABLE))
endif
ifneq (${FLASH_TYPE},)
$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
endif
ifneq (${XSPI_FLASH_SZ},)
$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
endif
ifneq (${QSPI_FLASH_SZ},)
$(eval $(call add_define_val,NXP_QSPI_FLASH_SIZE,${QSPI_FLASH_SZ}))
endif
ifneq (${NOR_FLASH_SZ},)
$(eval $(call add_define_val,NXP_NOR_FLASH_SIZE,${NOR_FLASH_SZ}))
endif
ifneq (${FSPI_ERASE_4K},)
$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
endif
ifneq (${NUM_OF_DDRC},)
$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
endif
ifeq (${CONFIG_DDR_NODIMM},1)
$(eval $(call add_define,CONFIG_DDR_NODIMM))
DDRC_NUM_DIMM := 1
endif
ifneq (${DDRC_NUM_DIMM},)
$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
endif
ifneq (${DDRC_NUM_CS},)
$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
endif
ifeq (${DDR_ADDR_DEC},yes)
$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
endif
ifeq (${DDR_ECC_EN},yes)
$(eval $(call add_define,CONFIG_DDR_ECC_EN))
endif
ifeq (${CONFIG_STATIC_DDR},1)
$(eval $(call add_define,CONFIG_STATIC_DDR))
endif
# Platform can control the base address for non-volatile storage.
#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
ifeq (${WARM_BOOT},yes)
$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
endif
# Selecting Boot Source for the TFA images.
define add_boot_mode_define
ifeq ($(1),qspi)
$$(eval $$(call SET_NXP_MAKE_FLAG,QSPI_NEEDED,BL2))
$$(eval $$(call add_define,QSPI_BOOT))
else ifeq ($(1),sd)
$$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
$$(eval $$(call add_define,SD_BOOT))
else ifeq ($(1),emmc)
$$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
$$(eval $$(call add_define,EMMC_BOOT))
else ifeq ($(1),nor)
$$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NOR_NEEDED,BL2))
$$(eval $$(call add_define,NOR_BOOT))
else ifeq ($(1),nand)
$$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NAND_NEEDED,BL2))
$$(eval $$(call add_define,NAND_BOOT))
else ifeq ($(1),flexspi_nor)
$$(eval $$(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2))
$$(eval $$(call add_define,FLEXSPI_NOR_BOOT))
else
$$(error $(PLAT) Cannot Support Boot Mode: $(BOOT_MODE))
endif
endef
ifneq (,$(findstring $(BOOT_MODE),$(SUPPORTED_BOOT_MODE)))
$(eval $(call add_boot_mode_define,$(strip $(BOOT_MODE))))
else
$(error $(PLAT) Un-supported Boot Mode = $(BOOT_MODE))
endif
plat/nxp/common/plat_make_helper/soc_common_def.mk 0 → 100644
View file @ f85ab341
# Copyright 2020-2021 NXP
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Adding SoC specific defines
ifneq (${CACHE_LINE},)
$(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE}))
$(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE)))))
$(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE)))
endif
ifeq (${INTERCONNECT}, "CCI400")
$(eval $(call add_define,NXP_HAS_${INTERCONNECT}))
ICNNCT_ID := 0x420
$(eval $(call add_define,ICNNCT_ID))
endif
ifeq (${INTERCONNECT}, "CCN508")
$(eval $(call add_define,NXP_HAS_CCN508))
endif
ifneq (${CHASSIS},)
$(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS}))
endif
ifneq (${PLAT_DDR_PHY},)
$(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY}))
endif
ifneq (${PHYS_SYS},)
$(eval $(call add_define,CONFIG_PHYS_64BIT))
endif
ifneq (${CSF_HDR_SZ},)
$(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ}))
endif
ifneq (${OCRAM_START_ADDR},)
$(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR}))
endif
ifneq (${OCRAM_SIZE},)
$(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE}))
endif
ifneq (${NXP_ROM_RSVD},)
$(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD}))
endif
ifneq (${BL2_BASE},)
$(eval $(call add_define_val,BL2_BASE,${BL2_BASE}))
endif
ifeq (${SEC_MEM_NON_COHERENT},yes)
$(eval $(call add_define,SEC_MEM_NON_COHERENT))
endif
ifneq (${NXP_ESDHC_ENDIANNESS},)
$(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS}))
endif
ifneq (${NXP_SFP_VER},)
$(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER}))
endif
ifneq (${NXP_SFP_ENDIANNESS},)
$(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS}))
endif
ifneq (${NXP_GPIO_ENDIANNESS},)
$(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS}))
endif
ifneq (${NXP_SNVS_ENDIANNESS},)
$(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS}))
endif
ifneq (${NXP_GUR_ENDIANNESS},)
$(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS}))
endif
ifneq (${NXP_FSPI_ENDIANNESS},)
$(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS}))
endif
ifneq (${NXP_SEC_ENDIANNESS},)
$(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS}))
endif
ifneq (${NXP_DDR_ENDIANNESS},)
$(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS}))
endif
ifneq (${NXP_QSPI_ENDIANNESS},)
$(eval $(call add_define,NXP_QSPI_${NXP_QSPI_ENDIANNESS}))
endif
ifneq (${NXP_SCFG_ENDIANNESS},)
$(eval $(call add_define,NXP_SCFG_${NXP_SCFG_ENDIANNESS}))
endif
ifneq (${NXP_IFC_ENDIANNESS},)
$(eval $(call add_define,NXP_IFC_${NXP_IFC_ENDIANNESS}))
endif
ifneq (${NXP_DDR_INTLV_256B},)
$(eval $(call add_define,NXP_DDR_INTLV_256B))
endif
ifneq (${PLAT_XLAT_TABLES_DYNAMIC},)
$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
endif
plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
View file @ f85ab341
......@@ -33,59 +33,19 @@ BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000
# config is enabled for future use cases.
FSPI_ERASE_4K := 0
# Platform specific features.
# Platform specific features.
WARM_BOOT := yes
# Adding platform specific defines
$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
ifeq (${POVDD_ENABLE},yes)
$(eval $(call add_define,CONFIG_POVDD_ENABLE))
endif
ifneq (${FLASH_TYPE},)
$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
endif
ifneq (${XSPI_FLASH_SZ},)
$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
endif
ifneq (${FSPI_ERASE_4K},)
$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
endif
ifneq (${NUM_OF_DDRC},)
$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
endif
ifneq (${DDRC_NUM_DIMM},)
$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
endif
ifneq (${DDRC_NUM_CS},)
$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
endif
ifeq (${DDR_ADDR_DEC},yes)
$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
endif
ifeq (${DDR_ECC_EN},yes)
$(eval $(call add_define,CONFIG_DDR_ECC_EN))
endif
# Platform can control the base address for non-volatile storage.
#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
ifeq (${WARM_BOOT},yes)
$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
endif
# Adding Platform files build files
# Adding Platform files build files
BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
${BOARD_PATH}/platform.c
# Adding SoC build info
SUPPORTED_BOOT_MODE := flexspi_nor \
sd \
emmc
# Adding platform board build info
include plat/nxp/common/plat_make_helper/plat_common_def.mk
# Adding SoC build info
include plat/nxp/soc-lx2160a/soc.mk
plat/nxp/soc-lx2160a/lx2160ardb/platform.mk
View file @ f85ab341
......@@ -36,56 +36,16 @@ FSPI_ERASE_4K := 0
# Platform specific features.
WARM_BOOT := no
# Adding platform specific defines
$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
ifeq (${POVDD_ENABLE},yes)
$(eval $(call add_define,CONFIG_POVDD_ENABLE))
endif
ifneq (${FLASH_TYPE},)
$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
endif
ifneq (${XSPI_FLASH_SZ},)
$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
endif
ifneq (${FSPI_ERASE_4K},)
$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
endif
ifneq (${NUM_OF_DDRC},)
$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
endif
ifneq (${DDRC_NUM_DIMM},)
$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
endif
ifneq (${DDRC_NUM_CS},)
$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
endif
ifeq (${DDR_ADDR_DEC},yes)
$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
endif
ifeq (${DDR_ECC_EN},yes)
$(eval $(call add_define,CONFIG_DDR_ECC_EN))
endif
# Platform can control the base address for non-volatile storage.
#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
ifeq (${WARM_BOOT},yes)
$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
endif
# Adding Platform files build files
BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
${BOARD_PATH}/platform.c
SUPPORTED_BOOT_MODE := flexspi_nor \
sd \
emmc
# Adding platform board build info
include plat/nxp/common/plat_make_helper/plat_common_def.mk
# Adding SoC build info
include plat/nxp/soc-lx2160a/soc.mk
plat/nxp/soc-lx2160a/lx2162aqds/platform.mk
View file @ f85ab341
......@@ -25,7 +25,7 @@ ERRATA_DDR_A011396 := 1
ERRATA_DDR_A050450 := 1
# On-Board Flash Details
# On-Board Flash Details
FLASH_TYPE := MT35XU512A
XSPI_FLASH_SZ := 0x10000000
NXP_XSPI_NOR_UNIT_SIZE := 0x20000
......@@ -34,59 +34,19 @@ BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000
# config is enabled for future use cases.
FSPI_ERASE_4K := 0
# Platform specific features.
# Platform specific features.
WARM_BOOT := yes
# Adding platform specific defines
$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
ifeq (${POVDD_ENABLE},yes)
$(eval $(call add_define,CONFIG_POVDD_ENABLE))
endif
ifneq (${FLASH_TYPE},)
$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
endif
ifneq (${XSPI_FLASH_SZ},)
$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
endif
ifneq (${FSPI_ERASE_4K},)
$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
endif
ifneq (${NUM_OF_DDRC},)
$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
endif
ifneq (${DDRC_NUM_DIMM},)
$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
endif
ifneq (${DDRC_NUM_CS},)
$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
endif
ifeq (${DDR_ADDR_DEC},yes)
$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
endif
ifeq (${DDR_ECC_EN},yes)
$(eval $(call add_define,CONFIG_DDR_ECC_EN))
endif
# Platform can control the base address for non-volatile storage.
#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
ifeq (${WARM_BOOT},yes)
$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
endif
# Adding Platform files build files
# Adding Platform files build files
BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
${BOARD_PATH}/platform.c
# Adding SoC build info
SUPPORTED_BOOT_MODE := flexspi_nor \
sd \
emmc
# Adding platform board build info
include plat/nxp/common/plat_make_helper/plat_common_def.mk
# Adding SoC build info
include plat/nxp/soc-lx2160a/soc.mk
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