Commit f8827c60 authored by Varun Wadekar's avatar Varun Wadekar
Browse files

Tegra210: support for secure physical timer



This patch enables on-chip timer1 interrupts for Tegra210 platforms.

Change-Id: Ic7417dc0e69264d7c28aa012fe2322cd30838f3e
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
parent d205cda6
...@@ -43,6 +43,11 @@ ...@@ -43,6 +43,11 @@
******************************************************************************/ ******************************************************************************/
#define SC7ENTRY_FW_HEADER_SIZE_BYTES U(0x400) #define SC7ENTRY_FW_HEADER_SIZE_BYTES U(0x400)
/*******************************************************************************
* Counter-timer physical secure timer PPI
******************************************************************************/
#define TEGRA210_TIMER1_IRQ 32
/******************************************************************************* /*******************************************************************************
* iRAM memory constants * iRAM memory constants
******************************************************************************/ ******************************************************************************/
......
...@@ -179,6 +179,8 @@ void plat_early_platform_setup(void) ...@@ -179,6 +179,8 @@ void plat_early_platform_setup(void)
/* Secure IRQs for Tegra186 */ /* Secure IRQs for Tegra186 */
static const interrupt_prop_t tegra210_interrupt_props[] = { static const interrupt_prop_t tegra210_interrupt_props[] = {
INTR_PROP_DESC(TEGRA210_TIMER1_IRQ, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, GIC_HIGHEST_SEC_PRIORITY, INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE), GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
}; };
......
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