aarch32: Fix L2CTRL definition for Cortex A57 and A72

Fixes ARM-software/tf-issues#495

Change-Id: I6a0aea78f670cc199873218a18af1d9cc2a6fafd
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

include/lib/cpus/aarch32/cortex_a57.h

@@ -55,7 +55,7 @@
 /*******************************************************************************
  * L2 Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A57_L2CTLR			p15, 1, c9, c0, 3
+#define CORTEX_A57_L2CTLR			p15, 1, c9, c0, 2
 
 #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
 #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT	6

include/lib/cpus/aarch32/cortex_a72.h

@@ -37,7 +37,7 @@
 /*******************************************************************************
  * L2 Control register specific definitions.
  ******************************************************************************/
-#define CORTEX_A72_L2CTLR			p15, 1, c9, c0, 3
+#define CORTEX_A72_L2CTLR			p15, 1, c9, c0, 2
 
 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT	6