Commit fb7d32e5 authored by Varun Wadekar's avatar Varun Wadekar
Browse files

Unique names for defines in the CPU libraries



This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.

NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE
TO START USING THE UPDATED NAMES
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
parent 6311f63d
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -22,47 +22,47 @@
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CPUECTLR p15, 1, c15 /* Instruction def. */
#define CORTEX_A53_ECTLR p15, 1, c15
#define CPUECTLR_SMP_BIT (1 << 6)
#define CORTEX_A53_ECTLR_SMP_BIT (1 << 6)
#define CPUECTLR_CPU_RET_CTRL_SHIFT 0
#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT 0
#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
#define CPUECTLR_FPU_RET_CTRL_SHIFT 3
#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT)
#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT 3
#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CPUMERRSR p15, 2, c15 /* Instruction def. */
#define CORTEX_A53_MERRSR p15, 2, c15
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CPUACTLR p15, 0, c15 /* Instruction def. */
#define CORTEX_A53_ACTLR p15, 0, c15
#define CPUACTLR_DTAH (1 << 24)
#define CORTEX_A53_ACTLR_DTAH (1 << 24)
/*******************************************************************************
* L2 Auxiliary Control register specific definitions.
******************************************************************************/
#define L2ACTLR p15, 1, c15, c0, 0 /* Instruction def. */
#define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0
#define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14)
#define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3)
#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14)
#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3)
/*******************************************************************************
* L2 Extended Control register specific definitions.
******************************************************************************/
#define L2ECTLR p15, 1, c9, c0, 3 /* Instruction def. */
#define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3
#define L2ECTLR_RET_CTRL_SHIFT 0
#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT 0
#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define L2MERRSR p15, 3, c15 /* Instruction def. */
#define CORTEX_A53_L2MERRSR p15, 3, c15
#endif /* __CORTEX_A53_H__ */
......@@ -22,58 +22,58 @@
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CPUECTLR p15, 1, c15 /* Instruction def. */
#define CORTEX_A57_ECTLR p15, 1, c15
#define CPUECTLR_SMP_BIT (1 << 6)
#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CORTEX_A57_ECTLR_SMP_BIT (1 << 6)
#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CPUECTLR_CPU_RET_CTRL_SHIFT 0
#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CPUMERRSR p15, 2, c15 /* Instruction def. */
#define CORTEX_A57_CPUMERRSR p15, 2, c15
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CPUACTLR p15, 0, c15 /* Instruction def. */
#define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59)
#define CPUACTLR_GRE_NGRE_AS_NGNRE (1 << 54)
#define CPUACTLR_DIS_OVERREAD (1 << 52)
#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
#define CPUACTLR_DCC_AS_DCCI (1 << 44)
#define CPUACTLR_FORCE_FPSCR_FLUSH (1 << 38)
#define CPUACTLR_DIS_STREAMING (3 << 27)
#define CPUACTLR_DIS_L1_STREAMING (3 << 25)
#define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4)
#define CORTEX_A57_ACTLR p15, 0, c15
#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (1 << 59)
#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (1 << 54)
#define CORTEX_A57_ACTLR_DIS_OVERREAD (1 << 52)
#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (1 << 49)
#define CORTEX_A57_ACTLR_DCC_AS_DCCI (1 << 44)
#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (1 << 38)
#define CORTEX_A57_ACTLR_DIS_STREAMING (3 << 27)
#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (3 << 25)
#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (1 << 4)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
#define L2CTLR p15, 1, c9, c0, 3 /* Instruction def. */
#define CORTEX_A57_L2CTLR p15, 1, c9, c0, 3
#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
/*******************************************************************************
* L2 Extended Control register specific definitions.
******************************************************************************/
#define L2ECTLR p15, 1, c9, c0, 3 /* Instruction def. */
#define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3
#define L2ECTLR_RET_CTRL_SHIFT 0
#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0
#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (0x7 << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define L2MERRSR p15, 3, c15 /* Instruction def. */
#define CORTEX_A57_L2MERRSR p15, 3, c15
#endif /* __CORTEX_A57_H__ */
......@@ -13,42 +13,42 @@
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CPUECTLR p15, 1, c15 /* Instruction def. */
#define CORTEX_A72_ECTLR p15, 1, c15
#define CPUECTLR_SMP_BIT (1 << 6)
#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6)
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CPUMERRSR p15, 2, c15 /* Instruction def. */
#define CORTEX_A72_MERRSR p15, 2, c15
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CPUACTLR p15, 0, c15 /* Instruction def. */
#define CORTEX_A72_ACTLR p15, 0, c15
#define CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
#define CPUACTLR_DCC_AS_DCCI (1 << 44)
#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49)
#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
#define L2CTLR p15, 1, c9, c0, 3 /* Instruction def. */
#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 3
#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define L2_TAG_RAM_LATENCY_2_CYCLES 0x1
#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define L2MERRSR p15, 3, c15 /* Instruction def. */
#define CORTEX_A72_L2MERRSR p15, 3, c15
#endif /* __CORTEX_A72_H__ */
/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -22,54 +22,54 @@
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1
#define CPUECTLR_SMP_BIT (1 << 6)
#define CORTEX_A53_ECTLR_SMP_BIT (1 << 6)
#define CPUECTLR_CPU_RET_CTRL_SHIFT 0
#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT 0
#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
#define CPUECTLR_FPU_RET_CTRL_SHIFT 3
#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT)
#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT 3
#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */
#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */
#define CORTEX_A53_ACTLR_EL1 S3_1_C15_C2_0
#define CPUACTLR_ENDCCASCI_SHIFT 44
#define CPUACTLR_ENDCCASCI (1 << CPUACTLR_ENDCCASCI_SHIFT)
#define CPUACTLR_RADIS_SHIFT 27
#define CPUACTLR_RADIS (3 << CPUACTLR_RADIS_SHIFT)
#define CPUACTLR_L1RADIS_SHIFT 25
#define CPUACTLR_L1RADIS (3 << CPUACTLR_L1RADIS_SHIFT)
#define CPUACTLR_DTAH_SHIFT 24
#define CPUACTLR_DTAH (1 << CPUACTLR_DTAH_SHIFT)
#define CORTEX_A53_ACTLR_ENDCCASCI_SHIFT 44
#define CORTEX_A53_ACTLR_ENDCCASCI (1 << CORTEX_A53_ACTLR_ENDCCASCI_SHIFT)
#define CORTEX_A53_ACTLR_RADIS_SHIFT 27
#define CORTEX_A53_ACTLR_RADIS (3 << CORTEX_A53_ACTLR_RADIS_SHIFT)
#define CORTEX_A53_ACTLR_L1RADIS_SHIFT 25
#define CORTEX_A53_ACTLR_L1RADIS (3 << CORTEX_A53_ACTLR_L1RADIS_SHIFT)
#define CORTEX_A53_ACTLR_DTAH_SHIFT 24
#define CORTEX_A53_ACTLR_DTAH (1 << CORTEX_A53_ACTLR_DTAH_SHIFT)
/*******************************************************************************
* L2 Auxiliary Control register specific definitions.
******************************************************************************/
#define L2ACTLR_EL1 S3_1_C15_C0_0 /* Instruction def. */
#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0
#define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14)
#define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3)
#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14)
#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3)
/*******************************************************************************
* L2 Extended Control register specific definitions.
******************************************************************************/
#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */
#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3
#define L2ECTLR_RET_CTRL_SHIFT 0
#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT 0
#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
#endif /* __CORTEX_A53_H__ */
......@@ -22,60 +22,60 @@
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
#define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1
#define CPUECTLR_SMP_BIT (1 << 6)
#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CORTEX_A57_ECTLR_SMP_BIT (1 << 6)
#define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CPUECTLR_CPU_RET_CTRL_SHIFT 0
#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT)
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT 0
#define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */
#define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */
#define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59)
#define CPUACTLR_GRE_NGRE_AS_NGNRE (1 << 54)
#define CPUACTLR_DIS_OVERREAD (1 << 52)
#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
#define CPUACTLR_DCC_AS_DCCI (1 << 44)
#define CPUACTLR_FORCE_FPSCR_FLUSH (1 << 38)
#define CPUACTLR_DIS_STREAMING (3 << 27)
#define CPUACTLR_DIS_L1_STREAMING (3 << 25)
#define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4)
#define CORTEX_A57_ACTLR_EL1 S3_1_C15_C2_0
#define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (1 << 59)
#define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (1 << 54)
#define CORTEX_A57_ACTLR_DIS_OVERREAD (1 << 52)
#define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (1 << 49)
#define CORTEX_A57_ACTLR_DCC_AS_DCCI (1 << 44)
#define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (1 << 38)
#define CORTEX_A57_ACTLR_DIS_STREAMING (3 << 27)
#define CORTEX_A57_ACTLR_DIS_L1_STREAMING (3 << 25)
#define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (1 << 4)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */
#define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2
#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
#define L2_ECC_PARITY_PROTECTION_BIT (1 << 21)
#define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (1 << 21)
/*******************************************************************************
* L2 Extended Control register specific definitions.
******************************************************************************/
#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */
#define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3
#define L2ECTLR_RET_CTRL_SHIFT 0
#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT)
#define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT 0
#define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (0x7 << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT)
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
#define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3
#endif /* __CORTEX_A57_H__ */
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -13,42 +13,42 @@
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
#define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1
#define CPUECTLR_SMP_BIT (1 << 6)
#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
#define CORTEX_A72_ECTLR_SMP_BIT (1 << 6)
#define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38)
#define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35)
#define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32)
/*******************************************************************************
* CPU Memory Error Syndrome register specific definitions.
******************************************************************************/
#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */
#define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */
#define CORTEX_A72_ACTLR_EL1 S3_1_C15_C2_0
#define CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
#define CPUACTLR_NO_ALLOC_WBWA (1 << 49)
#define CPUACTLR_DCC_AS_DCCI (1 << 44)
#define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56)
#define CORTEX_A72_ACTLR_NO_ALLOC_WBWA (1 << 49)
#define CORTEX_A72_ACTLR_DCC_AS_DCCI (1 << 44)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6
#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define L2_TAG_RAM_LATENCY_2_CYCLES 0x1
#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2
/*******************************************************************************
* L2 Memory Error Syndrome register specific definitions.
******************************************************************************/
#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
#define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3
#endif /* __CORTEX_A72_H__ */
......@@ -15,9 +15,9 @@
* ---------------------------------------------
*/
func cortex_a53_disable_smp
ldcopr16 r0, r1, CPUECTLR
bic64_imm r0, r1, CPUECTLR_SMP_BIT
stcopr16 r0, r1, CPUECTLR
ldcopr16 r0, r1, CORTEX_A53_ECTLR
bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT
stcopr16 r0, r1, CORTEX_A53_ECTLR
isb
dsb sy
bx lr
......@@ -32,9 +32,9 @@ func cortex_a53_reset_func
* Enable the SMP bit.
* ---------------------------------------------
*/
ldcopr16 r0, r1, CPUECTLR
orr64_imm r0, r1, CPUECTLR_SMP_BIT
stcopr16 r0, r1, CPUECTLR
ldcopr16 r0, r1, CORTEX_A53_ECTLR
orr64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT
stcopr16 r0, r1, CORTEX_A53_ECTLR
isb
bx lr
endfunc cortex_a53_reset_func
......
......@@ -16,9 +16,9 @@
* ---------------------------------------------
*/
func cortex_a57_disable_smp
ldcopr16 r0, r1, CPUECTLR
bic64_imm r0, r1, CPUECTLR_SMP_BIT
stcopr16 r0, r1, CPUECTLR
ldcopr16 r0, r1, CORTEX_A57_ECTLR
bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT
stcopr16 r0, r1, CORTEX_A57_ECTLR
bx lr
endfunc cortex_a57_disable_smp
......@@ -28,11 +28,11 @@ endfunc cortex_a57_disable_smp
* ---------------------------------------------
*/
func cortex_a57_disable_l2_prefetch
ldcopr16 r0, r1, CPUECTLR
orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT
bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \
CPUECTLR_L2_DPFTCH_DIST_MASK)
stcopr16 r0, r1, CPUECTLR
ldcopr16 r0, r1, CORTEX_A57_ECTLR
orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT
bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \
CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK)
stcopr16 r0, r1, CORTEX_A57_ECTLR
isb
dsb ish
bx lr
......@@ -59,9 +59,9 @@ func cortex_a57_reset_func
* Enable the SMP bit.
* ---------------------------------------------
*/
ldcopr16 r0, r1, CPUECTLR
orr64_imm r0, r1, CPUECTLR_SMP_BIT
stcopr16 r0, r1, CPUECTLR
ldcopr16 r0, r1, CORTEX_A57_ECTLR
orr64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT
stcopr16 r0, r1, CORTEX_A57_ECTLR
isb
bx lr
endfunc cortex_a57_reset_func
......
......@@ -15,11 +15,11 @@
* ---------------------------------------------
*/
func cortex_a72_disable_l2_prefetch
ldcopr16 r0, r1, CPUECTLR
orr64_imm r0, r1, CPUECTLR_DIS_TWD_ACC_PFTCH_BIT
bic64_imm r0, r1, (CPUECTLR_L2_IPFTCH_DIST_MASK | \
CPUECTLR_L2_DPFTCH_DIST_MASK)
stcopr16 r0, r1, CPUECTLR
ldcopr16 r0, r1, CORTEX_A72_ECTLR
orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \
CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK)
stcopr16 r0, r1, CORTEX_A72_ECTLR
isb
bx lr
endfunc cortex_a72_disable_l2_prefetch
......@@ -29,9 +29,9 @@ endfunc cortex_a72_disable_l2_prefetch
* ---------------------------------------------
*/
func cortex_a72_disable_hw_prefetcher
ldcopr16 r0, r1, CPUACTLR
orr64_imm r0, r1, CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
stcopr16 r0, r1, CPUACTLR
ldcopr16 r0, r1, CORTEX_A72_ACTLR
orr64_imm r0, r1, CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH
stcopr16 r0, r1, CORTEX_A72_ACTLR
isb
dsb ish
bx lr
......@@ -43,9 +43,9 @@ endfunc cortex_a72_disable_hw_prefetcher
* ---------------------------------------------
*/
func cortex_a72_disable_smp
ldcopr16 r0, r1, CPUECTLR
bic64_imm r0, r1, CPUECTLR_SMP_BIT
stcopr16 r0, r1, CPUECTLR
ldcopr16 r0, r1, CORTEX_A72_ECTLR
bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT
stcopr16 r0, r1, CORTEX_A72_ECTLR
bx lr
endfunc cortex_a72_disable_smp
......@@ -70,9 +70,9 @@ func cortex_a72_reset_func
* Enable the SMP bit.
* ---------------------------------------------
*/
ldcopr16 r0, r1, CPUECTLR
orr64_imm r0, r1, CPUECTLR_SMP_BIT
stcopr16 r0, r1, CPUECTLR
ldcopr16 r0, r1, CORTEX_A72_ECTLR
orr64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT
stcopr16 r0, r1, CORTEX_A72_ECTLR
isb
bx lr
endfunc cortex_a72_reset_func
......
......@@ -33,9 +33,9 @@ endfunc cortex_a53_disable_dcache
* ---------------------------------------------
*/
func cortex_a53_disable_smp
mrs x0, CPUECTLR_EL1
bic x0, x0, #CPUECTLR_SMP_BIT
msr CPUECTLR_EL1, x0
mrs x0, CORTEX_A53_ECTLR_EL1
bic x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
msr CORTEX_A53_ECTLR_EL1, x0
isb
dsb sy
ret
......@@ -56,10 +56,10 @@ func errata_a53_826319_wa
mov x17, x30
bl check_errata_826319
cbz x0, 1f
mrs x1, L2ACTLR_EL1
bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN
orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH
msr L2ACTLR_EL1, x1
mrs x1, CORTEX_A53_L2ACTLR_EL1
bic x1, x1, #CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN
orr x1, x1, #CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH
msr CORTEX_A53_L2ACTLR_EL1, x1
1:
ret x17
endfunc errata_a53_826319_wa
......@@ -93,9 +93,9 @@ func a53_disable_non_temporal_hint
mov x17, x30
bl check_errata_disable_non_temporal_hint
cbz x0, 1f
mrs x1, CPUACTLR_EL1
orr x1, x1, #CPUACTLR_DTAH
msr CPUACTLR_EL1, x1
mrs x1, CORTEX_A53_ACTLR_EL1
orr x1, x1, #CORTEX_A53_ACTLR_DTAH
msr CORTEX_A53_ACTLR_EL1, x1
1:
ret x17
endfunc a53_disable_non_temporal_hint
......@@ -126,9 +126,9 @@ func errata_a53_855873_wa
bl check_errata_855873
cbz x0, 1f
mrs x1, CPUACTLR_EL1
orr x1, x1, #CPUACTLR_ENDCCASCI
msr CPUACTLR_EL1, x1
mrs x1, CORTEX_A53_ACTLR_EL1
orr x1, x1, #CORTEX_A53_ACTLR_ENDCCASCI
msr CORTEX_A53_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a53_855873_wa
......@@ -168,9 +168,9 @@ func cortex_a53_reset_func
* Enable the SMP bit.
* ---------------------------------------------
*/
mrs x0, CPUECTLR_EL1
orr x0, x0, #CPUECTLR_SMP_BIT
msr CPUECTLR_EL1, x0
mrs x0, CORTEX_A53_ECTLR_EL1
orr x0, x0, #CORTEX_A53_ECTLR_SMP_BIT
msr CORTEX_A53_ECTLR_EL1, x0
isb
ret x19
endfunc cortex_a53_reset_func
......@@ -275,10 +275,10 @@ cortex_a53_regs: /* The ascii list of register names to be reported */
func cortex_a53_cpu_reg_dump
adr x6, cortex_a53_regs
mrs x8, CPUECTLR_EL1
mrs x9, CPUMERRSR_EL1
mrs x10, L2MERRSR_EL1
mrs x11, CPUACTLR_EL1
mrs x8, CORTEX_A53_ECTLR_EL1
mrs x9, CORTEX_A53_MERRSR_EL1
mrs x10, CORTEX_A53_L2MERRSR_EL1
mrs x11, CORTEX_A53_ACTLR_EL1
ret
endfunc cortex_a53_cpu_reg_dump
......
......@@ -29,12 +29,12 @@ endfunc cortex_a57_disable_dcache
* ---------------------------------------------
*/
func cortex_a57_disable_l2_prefetch
mrs x0, CPUECTLR_EL1
orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT
mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK
orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK
mrs x0, CORTEX_A57_ECTLR_EL1
orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT
mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK
orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK
bic x0, x0, x1
msr CPUECTLR_EL1, x0
msr CORTEX_A57_ECTLR_EL1, x0
isb
dsb ish
ret
......@@ -45,9 +45,9 @@ endfunc cortex_a57_disable_l2_prefetch
* ---------------------------------------------
*/
func cortex_a57_disable_smp
mrs x0, CPUECTLR_EL1
bic x0, x0, #CPUECTLR_SMP_BIT
msr CPUECTLR_EL1, x0
mrs x0, CORTEX_A57_ECTLR_EL1
bic x0, x0, #CORTEX_A57_ECTLR_SMP_BIT
msr CORTEX_A57_ECTLR_EL1, x0
ret
endfunc cortex_a57_disable_smp
......@@ -78,9 +78,9 @@ func errata_a57_806969_wa
mov x17, x30
bl check_errata_806969
cbz x0, 1f
mrs x1, CPUACTLR_EL1
orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA
msr CPUACTLR_EL1, x1
mrs x1, CORTEX_A57_ACTLR_EL1
orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA
msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_806969_wa
......@@ -120,9 +120,9 @@ func errata_a57_813420_wa
mov x17, x30
bl check_errata_813420
cbz x0, 1f
mrs x1, CPUACTLR_EL1
orr x1, x1, #CPUACTLR_DCC_AS_DCCI
msr CPUACTLR_EL1, x1
mrs x1, CORTEX_A57_ACTLR_EL1
orr x1, x1, #CORTEX_A57_ACTLR_DCC_AS_DCCI
msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_813420_wa
......@@ -150,9 +150,9 @@ func a57_disable_ldnp_overread
mov x17, x30
bl check_errata_disable_ldnp_overread
cbz x0, 1f
mrs x1, CPUACTLR_EL1
orr x1, x1, #CPUACTLR_DIS_OVERREAD
msr CPUACTLR_EL1, x1
mrs x1, CORTEX_A57_ACTLR_EL1
orr x1, x1, #CORTEX_A57_ACTLR_DIS_OVERREAD
msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc a57_disable_ldnp_overread
......@@ -177,9 +177,9 @@ func errata_a57_826974_wa
mov x17, x30
bl check_errata_826974
cbz x0, 1f
mrs x1, CPUACTLR_EL1
orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB
msr CPUACTLR_EL1, x1
mrs x1, CORTEX_A57_ACTLR_EL1
orr x1, x1, #CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB
msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_826974_wa
......@@ -204,9 +204,9 @@ func errata_a57_826977_wa
mov x17, x30
bl check_errata_826977
cbz x0, 1f
mrs x1, CPUACTLR_EL1
orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE
msr CPUACTLR_EL1, x1
mrs x1, CORTEX_A57_ACTLR_EL1
orr x1, x1, #CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE
msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_826977_wa
......@@ -231,15 +231,16 @@ func errata_a57_828024_wa
mov x17, x30
bl check_errata_828024
cbz x0, 1f
mrs x1, CPUACTLR_EL1
mrs x1, CORTEX_A57_ACTLR_EL1
/*
* Setting the relevant bits in CPUACTLR_EL1 has to be done in 2
* instructions here because the resulting bitmask doesn't fit in a
* 16-bit value so it cannot be encoded in a single instruction.
*/
orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA
orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING)
msr CPUACTLR_EL1, x1
orr x1, x1, #CORTEX_A57_ACTLR_NO_ALLOC_WBWA
orr x1, x1, #(CORTEX_A57_ACTLR_DIS_L1_STREAMING | \
CORTEX_A57_ACTLR_DIS_STREAMING)
msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_828024_wa
......@@ -264,9 +265,9 @@ func errata_a57_829520_wa
mov x17, x30
bl check_errata_829520
cbz x0, 1f
mrs x1, CPUACTLR_EL1
orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR
msr CPUACTLR_EL1, x1
mrs x1, CORTEX_A57_ACTLR_EL1
orr x1, x1, #CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR
msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_829520_wa
......@@ -291,9 +292,9 @@ func errata_a57_833471_wa
mov x17, x30
bl check_errata_833471
cbz x0, 1f
mrs x1, CPUACTLR_EL1
orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH
msr CPUACTLR_EL1, x1
mrs x1, CORTEX_A57_ACTLR_EL1
orr x1, x1, #CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH
msr CORTEX_A57_ACTLR_EL1, x1
1:
ret x17
endfunc errata_a57_833471_wa
......@@ -357,9 +358,9 @@ func cortex_a57_reset_func
* Enable the SMP bit.
* ---------------------------------------------
*/
mrs x0, CPUECTLR_EL1
orr x0, x0, #CPUECTLR_SMP_BIT
msr CPUECTLR_EL1, x0
mrs x0, CORTEX_A57_ECTLR_EL1
orr x0, x0, #CORTEX_A57_ECTLR_SMP_BIT
msr CORTEX_A57_ECTLR_EL1, x0
isb
ret x19
endfunc cortex_a57_reset_func
......@@ -503,9 +504,9 @@ cortex_a57_regs: /* The ascii list of register names to be reported */
func cortex_a57_cpu_reg_dump
adr x6, cortex_a57_regs
mrs x8, CPUECTLR_EL1
mrs x9, CPUMERRSR_EL1
mrs x10, L2MERRSR_EL1
mrs x8, CORTEX_A57_ECTLR_EL1
mrs x9, CORTEX_A57_MERRSR_EL1
mrs x10, CORTEX_A57_L2MERRSR_EL1
ret
endfunc cortex_a57_cpu_reg_dump
......
......@@ -27,12 +27,12 @@ endfunc cortex_a72_disable_dcache
* ---------------------------------------------
*/
func cortex_a72_disable_l2_prefetch
mrs x0, CPUECTLR_EL1
orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT
mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK
orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK
mrs x0, CORTEX_A72_ECTLR_EL1
orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK
orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK
bic x0, x0, x1
msr CPUECTLR_EL1, x0
msr CORTEX_A72_ECTLR_EL1, x0
isb
ret
endfunc cortex_a72_disable_l2_prefetch
......@@ -42,9 +42,9 @@ endfunc cortex_a72_disable_l2_prefetch
* ---------------------------------------------
*/
func cortex_a72_disable_hw_prefetcher
mrs x0, CPUACTLR_EL1
orr x0, x0, #CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
msr CPUACTLR_EL1, x0
mrs x0, CORTEX_A72_ACTLR_EL1
orr x0, x0, #CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH
msr CORTEX_A72_ACTLR_EL1, x0
isb
dsb ish
ret
......@@ -55,9 +55,9 @@ endfunc cortex_a72_disable_hw_prefetcher
* ---------------------------------------------
*/
func cortex_a72_disable_smp
mrs x0, CPUECTLR_EL1
bic x0, x0, #CPUECTLR_SMP_BIT
msr CPUECTLR_EL1, x0
mrs x0, CORTEX_A72_ECTLR_EL1
bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
msr CORTEX_A72_ECTLR_EL1, x0
ret
endfunc cortex_a72_disable_smp
......@@ -82,9 +82,9 @@ func cortex_a72_reset_func
* As a bare minimum enable the SMP bit.
* ---------------------------------------------
*/
mrs x0, CPUECTLR_EL1
orr x0, x0, #CPUECTLR_SMP_BIT
msr CPUECTLR_EL1, x0
mrs x0, CORTEX_A72_ECTLR_EL1
orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
msr CORTEX_A72_ECTLR_EL1, x0
isb
ret
endfunc cortex_a72_reset_func
......@@ -211,9 +211,9 @@ cortex_a72_regs: /* The ascii list of register names to be reported */
func cortex_a72_cpu_reg_dump
adr x6, cortex_a72_regs
mrs x8, CPUECTLR_EL1
mrs x9, CPUMERRSR_EL1
mrs x10, L2MERRSR_EL1
mrs x8, CORTEX_A72_ECTLR_EL1
mrs x9, CORTEX_A72_MERRSR_EL1
mrs x10, CORTEX_A72_L2MERRSR_EL1
ret
endfunc cortex_a72_cpu_reg_dump
......
......@@ -86,9 +86,9 @@ func JUNO_HANDLER(0)
* Cortex-A57 specific settings
* --------------------------------------------------------------------
*/
mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
(L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
msr L2CTLR_EL1, x0
mov x0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
(CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT))
msr CORTEX_A57_L2CTLR_EL1, x0
1:
isb
ret
......@@ -123,8 +123,8 @@ A57:
* Cortex-A57 specific settings
* --------------------------------------------------------------------
*/
mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT)
msr L2CTLR_EL1, x0
mov x0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT)
msr CORTEX_A57_L2CTLR_EL1, x0
isb
ret
endfunc JUNO_HANDLER(1)
......@@ -157,9 +157,9 @@ A72:
* Cortex-A72 specific settings
* --------------------------------------------------------------------
*/
mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
(L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT))
msr L2CTLR_EL1, x0
mov x0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
(CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES << CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT))
msr CORTEX_A57_L2CTLR_EL1, x0
isb
ret
endfunc JUNO_HANDLER(2)
......
......@@ -20,11 +20,11 @@ func pm_asm_code
mov x0, 0
msr oslar_el1, x0
mrs x0, CPUACTLR_EL1
bic x0, x0, #(CPUACTLR_RADIS | CPUACTLR_L1RADIS)
mrs x0, CORTEX_A53_ACTLR_EL1
bic x0, x0, #(CORTEX_A53_ACTLR_RADIS | CORTEX_A53_ACTLR_L1RADIS)
orr x0, x0, #0x180000
orr x0, x0, #0xe000
msr CPUACTLR_EL1, x0
msr CORTEX_A53_ACTLR_EL1, x0
mrs x3, actlr_el3
orr x3, x3, #ACTLR_EL3_L2ECTLR_BIT
......
......@@ -68,18 +68,18 @@
* Enable processor retention
* ---------------------------
*/
mrs x0, L2ECTLR_EL1
mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT
bic x0, x0, #L2ECTLR_RET_CTRL_MASK
mrs x0, CORTEX_A57_L2ECTLR_EL1
mov x1, #RETENTION_ENTRY_TICKS_512
bic x0, x0, #CORTEX_A57_L2ECTLR_RET_CTRL_MASK
orr x0, x0, x1
msr L2ECTLR_EL1, x0
msr CORTEX_A57_L2ECTLR_EL1, x0
isb
mrs x0, CPUECTLR_EL1
mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT
bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK
mrs x0, CORTEX_A57_ECTLR_EL1
mov x1, #RETENTION_ENTRY_TICKS_512
bic x0, x0, #CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK
orr x0, x0, x1
msr CPUECTLR_EL1, x0
msr CORTEX_A57_ECTLR_EL1, x0
isb
/* -------------------------------------------------------
......@@ -98,11 +98,11 @@
adr x0, tegra_enable_l2_ecc_parity_prot
ldr x0, [x0]
cbz x0, 1f
mrs x0, L2CTLR_EL1
and x1, x0, #L2_ECC_PARITY_PROTECTION_BIT
mrs x0, CORTEX_A57_L2CTLR_EL1
and x1, x0, #CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT
cbnz x1, 1f
orr x0, x0, #L2_ECC_PARITY_PROTECTION_BIT
msr L2CTLR_EL1, x0
orr x0, x0, #CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT
msr CORTEX_A57_L2CTLR_EL1, x0
isb
/* --------------------------------
......@@ -317,18 +317,18 @@ func tegra_secure_entrypoint
* entries from the branch predictor array.
* -------------------------------------------------------
*/
mrs x0, CPUACTLR_EL1
mrs x0, CORTEX_A57_ACTLR_EL1
orr x0, x0, #1
msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */
msr CORTEX_A57_ACTLR_EL1, x0 /* invalidate BTB and I$ together */
dsb sy
isb
ic iallu /* actual invalidate */
dsb sy
isb
mrs x0, CPUACTLR_EL1
mrs x0, CORTEX_A57_ACTLR_EL1
bic x0, x0, #1
msr CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
msr CORTEX_A57_ACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */
dsb sy
isb
......@@ -352,7 +352,7 @@ func tegra_secure_entrypoint
msr oslar_el1, x0 /* os lock stays 0 across warm reset */
mov x3, #3
movz x4, #0x8000, lsl #48
msr CPUACTLR_EL1, x4 /* turn off RCG */
msr CORTEX_A57_ACTLR_EL1, x4 /* turn off RCG */
isb
msr rmr_el3, x3 /* request warm reset */
isb
......
......@@ -22,7 +22,7 @@
#include <tegra_private.h>
#include <xlat_tables.h>
DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1)
DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, CORTEX_A57_L2CTLR_EL1)
extern uint64_t tegra_enable_l2_ecc_parity_prot;
/*******************************************************************************
......@@ -172,7 +172,7 @@ void plat_early_platform_setup(void)
if (val >= TEGRA186_VER_A02P) {
val = read_l2ctlr_el1();
val |= L2_ECC_PARITY_PROTECTION_BIT;
val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
write_l2ctlr_el1(val);
/*
......
......@@ -43,9 +43,9 @@ handler_a72:
* Set the L2 Data RAM latency for Cortex-A72.
* Set the L2 Tag RAM latency to for Cortex-A72.
*/
mov x0, #((5 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
(0x1 << 5))
msr L2CTLR_EL1, x0
msr CORTEX_A72_L2CTLR_EL1, x0
isb
handler_end:
ret
......
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