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Unverified Commit fbf35335 authored by Antonio Niño Díaz's avatar Antonio Niño Díaz Committed by GitHub
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Merge pull request #1767 from Yann-lms/updates_stm32mp1 

Updates for STM32MP1
parents f0bfe15b 7747356d
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include/drivers/st/stm32mp1_ddr_regs.h
View file @ fbf35335
/*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
......@@ -247,11 +247,14 @@ struct stm32mp1_ddrphy {
#define DDRCTRL_DBGSTAT 0x310
#define DDRCTRL_SWCTL 0x320
#define DDRCTRL_SWSTAT 0x324
#define DDRCTRL_PSTAT 0x3FC
#define DDRCTRL_PCTRL_0 0x490
#define DDRCTRL_PCTRL_1 0x540
/* DDR Controller Register fields */
#define DDRCTRL_MSTR_DDR3 BIT(0)
#define DDRCTRL_MSTR_LPDDR2 BIT(2)
#define DDRCTRL_MSTR_LPDDR3 BIT(3)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK GENMASK(13, 12)
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_FULL 0
#define DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF BIT(12)
......@@ -269,7 +272,7 @@ struct stm32mp1_ddrphy {
/* Only one rank supported */
#define DDRCTRL_MRCTRL0_MR_RANK_SHIFT 4
#define DDRCTRL_MRCTRL0_MR_RANK_ALL \
(0x1U << DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
BIT(DDRCTRL_MRCTRL0_MR_RANK_SHIFT)
#define DDRCTRL_MRCTRL0_MR_ADDR_SHIFT 12
#define DDRCTRL_MRCTRL0_MR_ADDR_MASK GENMASK(15, 12)
#define DDRCTRL_MRCTRL0_MR_WR BIT(31)
......@@ -367,6 +370,7 @@ struct stm32mp1_ddrphy {
#define DDRPHYC_DLLGCR_BPS200 BIT(23)
#define DDRPHYC_ACDLLCR_DLLSRST BIT(30)
#define DDRPHYC_ACDLLCR_DLLDIS BIT(31)
#define DDRPHYC_PTR0_TDLLSRST_OFFSET 0
......
include/drivers/st/stm32mp1_rcc.h
View file @ fbf35335
/*
* Copyright (c) 2015-2018, STMicroelectronics - All Rights Reserved
* Copyright (c) 2015-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -68,6 +68,14 @@
#define RCC_MP_AHB6ENCLRR U(0x21C)
#define RCC_MP_TZAHB6ENSETR U(0x220)
#define RCC_MP_TZAHB6ENCLRR U(0x224)
#define RCC_MC_APB4ENSETR U(0x280)
#define RCC_MC_APB4ENCLRR U(0x284)
#define RCC_MC_APB5ENSETR U(0x288)
#define RCC_MC_APB5ENCLRR U(0x28C)
#define RCC_MC_AHB5ENSETR U(0x290)
#define RCC_MC_AHB5ENCLRR U(0x294)
#define RCC_MC_AHB6ENSETR U(0x298)
#define RCC_MC_AHB6ENCLRR U(0x29C)
#define RCC_MP_APB4LPENSETR U(0x300)
#define RCC_MP_APB4LPENCLRR U(0x304)
#define RCC_MP_APB5LPENSETR U(0x308)
......@@ -78,6 +86,14 @@
#define RCC_MP_AHB6LPENCLRR U(0x31C)
#define RCC_MP_TZAHB6LPENSETR U(0x320)
#define RCC_MP_TZAHB6LPENCLRR U(0x324)
#define RCC_MC_APB4LPENSETR U(0x380)
#define RCC_MC_APB4LPENCLRR U(0x384)
#define RCC_MC_APB5LPENSETR U(0x388)
#define RCC_MC_APB5LPENCLRR U(0x38C)
#define RCC_MC_AHB5LPENSETR U(0x390)
#define RCC_MC_AHB5LPENCLRR U(0x394)
#define RCC_MC_AHB6LPENSETR U(0x398)
#define RCC_MC_AHB6LPENCLRR U(0x39C)
#define RCC_BR_RSTSCLRR U(0x400)
#define RCC_MP_GRSTCSETR U(0x404)
#define RCC_MP_RSTSCLRR U(0x408)
......@@ -162,6 +178,22 @@
#define RCC_MP_AHB4ENCLRR U(0xA2C)
#define RCC_MP_MLAHBENSETR U(0xA38)
#define RCC_MP_MLAHBENCLRR U(0xA3C)
#define RCC_MC_APB1ENSETR U(0xA80)
#define RCC_MC_APB1ENCLRR U(0xA84)
#define RCC_MC_APB2ENSETR U(0xA88)
#define RCC_MC_APB2ENCLRR U(0xA8C)
#define RCC_MC_APB3ENSETR U(0xA90)
#define RCC_MC_APB3ENCLRR U(0xA94)
#define RCC_MC_AHB2ENSETR U(0xA98)
#define RCC_MC_AHB2ENCLRR U(0xA9C)
#define RCC_MC_AHB3ENSETR U(0xAA0)
#define RCC_MC_AHB3ENCLRR U(0xAA4)
#define RCC_MC_AHB4ENSETR U(0xAA8)
#define RCC_MC_AHB4ENCLRR U(0xAAC)
#define RCC_MC_AXIMENSETR U(0xAB0)
#define RCC_MC_AXIMENCLRR U(0xAB4)
#define RCC_MC_MLAHBENSETR U(0xAB8)
#define RCC_MC_MLAHBENCLRR U(0xABC)
#define RCC_MP_APB1LPENSETR U(0xB00)
#define RCC_MP_APB1LPENCLRR U(0xB04)
#define RCC_MP_APB2LPENSETR U(0xB08)
......@@ -178,10 +210,31 @@
#define RCC_MP_AXIMLPENCLRR U(0xB34)
#define RCC_MP_MLAHBLPENSETR U(0xB38)
#define RCC_MP_MLAHBLPENCLRR U(0xB3C)
#define RCC_MC_APB1LPENSETR U(0xB80)
#define RCC_MC_APB1LPENCLRR U(0xB84)
#define RCC_MC_APB2LPENSETR U(0xB88)
#define RCC_MC_APB2LPENCLRR U(0xB8C)
#define RCC_MC_APB3LPENSETR U(0xB90)
#define RCC_MC_APB3LPENCLRR U(0xB94)
#define RCC_MC_AHB2LPENSETR U(0xB98)
#define RCC_MC_AHB2LPENCLRR U(0xB9C)
#define RCC_MC_AHB3LPENSETR U(0xBA0)
#define RCC_MC_AHB3LPENCLRR U(0xBA4)
#define RCC_MC_AHB4LPENSETR U(0xBA8)
#define RCC_MC_AHB4LPENCLRR U(0xBAC)
#define RCC_MC_AXIMLPENSETR U(0xBB0)
#define RCC_MC_AXIMLPENCLRR U(0xBB4)
#define RCC_MC_MLAHBLPENSETR U(0xBB8)
#define RCC_MC_MLAHBLPENCLRR U(0xBBC)
#define RCC_MC_RSTSCLRR U(0xC00)
#define RCC_MC_CIER U(0xC14)
#define RCC_MC_CIFR U(0xC18)
#define RCC_VERR U(0xFF4)
#define RCC_IDR U(0xFF8)
#define RCC_SIDR U(0xFFC)
#define RCC_OFFSET_MASK GENMASK(11, 0)
/* Values for RCC_TZCR register */
#define RCC_TZCR_TZEN BIT(0)
......@@ -221,6 +274,9 @@
#define RCC_MPUDIV_MASK GENMASK(2, 0)
#define RCC_AXIDIV_MASK GENMASK(2, 0)
/* Used for TIMER Prescaler */
#define RCC_TIMGXPRER_TIMGXPRE BIT(0)
/* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
#define RCC_MP_ENCLRR_OFFSET U(4)
......@@ -228,6 +284,7 @@
#define RCC_BDCR_LSEON BIT(0)
#define RCC_BDCR_LSEBYP BIT(1)
#define RCC_BDCR_LSERDY BIT(2)
#define RCC_BDCR_DIGBYP BIT(3)
#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
#define RCC_BDCR_LSEDRV_SHIFT 4
#define RCC_BDCR_LSECSSON BIT(8)
......@@ -243,6 +300,7 @@
/* Used for all RCC_PLL<n>CR registers */
#define RCC_PLLNCR_PLLON BIT(0)
#define RCC_PLLNCR_PLLRDY BIT(1)
#define RCC_PLLNCR_SSCG_CTRL BIT(2)
#define RCC_PLLNCR_DIVPEN BIT(4)
#define RCC_PLLNCR_DIVQEN BIT(5)
#define RCC_PLLNCR_DIVREN BIT(6)
......@@ -281,8 +339,12 @@
/* Used for RCC_OCENSETR and RCC_OCENCLRR registers */
#define RCC_OCENR_HSION BIT(0)
#define RCC_OCENR_HSIKERON BIT(1)
#define RCC_OCENR_CSION BIT(4)
#define RCC_OCENR_CSIKERON BIT(5)
#define RCC_OCENR_DIGBYP BIT(7)
#define RCC_OCENR_HSEON BIT(8)
#define RCC_OCENR_HSEKERON BIT(9)
#define RCC_OCENR_HSEBYP BIT(10)
#define RCC_OCENR_HSECSSON BIT(11)
......@@ -319,6 +381,16 @@
/* Fields of RCC_HSICFGR register */
#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
#define RCC_HSICFGR_HSITRIM_SHIFT 8
#define RCC_HSICFGR_HSITRIM_MASK GENMASK(14, 8)
#define RCC_HSICFGR_HSICAL_SHIFT 16
#define RCC_HSICFGR_HSICAL_MASK GENMASK(27, 16)
/* Fields of RCC_CSICFGR register */
#define RCC_CSICFGR_CSITRIM_SHIFT 8
#define RCC_CSICFGR_CSITRIM_MASK GENMASK(12, 8)
#define RCC_CSICFGR_CSICAL_SHIFT 16
#define RCC_CSICFGR_CSICAL_MASK GENMASK(23, 16)
/* Used for RCC_MCO related operations */
#define RCC_MCOCFG_MCOON BIT(12)
......@@ -330,22 +402,36 @@
#define RCC_DBGCFGR_DBGCKEN BIT(8)
/* RCC register fields for reset reasons */
#define RCC_MP_RSTSCLRR_PORRSTF BIT(0)
#define RCC_MP_RSTSCLRR_BORRSTF BIT(1)
#define RCC_MP_RSTSCLRR_PADRSTF BIT(2)
#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3)
#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4)
#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6)
#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8)
#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9)
#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11)
#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12)
#define RCC_MP_RSTSCLRR_PORRSTF BIT(0)
#define RCC_MP_RSTSCLRR_BORRSTF BIT(1)
#define RCC_MP_RSTSCLRR_PADRSTF BIT(2)
#define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3)
#define RCC_MP_RSTSCLRR_VCORERSTF BIT(4)
#define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6)
#define RCC_MP_RSTSCLRR_MCSYSRSTF BIT(7)
#define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8)
#define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9)
#define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11)
#define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12)
#define RCC_MP_RSTSCLRR_MPUP0RSTF BIT(13)
#define RCC_MP_RSTSCLRR_MPUP1RSTF BIT(14)
/* Global Reset Register */
#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
/* Clock Source Interrupt Flag Register */
#define RCC_MP_CIFR_MASK U(0x110F1F)
#define RCC_MP_CIFR_LSIRDYF BIT(0)
#define RCC_MP_CIFR_LSERDYF BIT(1)
#define RCC_MP_CIFR_HSIRDYF BIT(2)
#define RCC_MP_CIFR_HSERDYF BIT(3)
#define RCC_MP_CIFR_CSIRDYF BIT(4)
#define RCC_MP_CIFR_PLL1DYF BIT(8)
#define RCC_MP_CIFR_PLL2DYF BIT(9)
#define RCC_MP_CIFR_PLL3DYF BIT(10)
#define RCC_MP_CIFR_PLL4DYF BIT(11)
#define RCC_MP_CIFR_WKUPF BIT(20)
/* Stop Request Set Register */
......@@ -362,7 +448,29 @@
/* Values of RCC_MP_APB1ENSETR register */
#define RCC_MP_APB1ENSETR_UART4EN BIT(16)
/* Values of RCC_MP_APB5ENSETR register */
#define RCC_MP_APB5ENSETR_SPI6EN BIT(0)
#define RCC_MP_APB5ENSETR_I2C4EN BIT(2)
#define RCC_MP_APB5ENSETR_I2C6EN BIT(3)
#define RCC_MP_APB5ENSETR_USART1EN BIT(4)
#define RCC_MP_APB5ENSETR_RTCAPBEN BIT(8)
#define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(15)
/* Values of RCC_MP_AHB4ENSETR register */
#define RCC_MP_AHB4ENSETR_GPIOGEN BIT(6)
#define RCC_MP_AHB4ENSETR_GPIOHEN BIT(7)
/* Values of RCC_MP_AHB5ENSETR register */
#define RCC_MP_AHB5ENSETR_GPIOZEN BIT(0)
#define RCC_MP_AHB5ENSETR_CRYP1EN BIT(4)
#define RCC_MP_AHB5ENSETR_HASH1EN BIT(5)
#define RCC_MP_AHB5ENSETR_RNG1EN BIT(6)
/* Values of RCC_MP_IWDGFZSETR register */
#define RCC_MP_IWDGFZSETR_IWDG1 BIT(0)
#define RCC_MP_IWDGFZSETR_IWDG2 BIT(1)
/* Values of RCC_PWRLPDLYCR register */
#define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK(21, 0)
#endif /* STM32MP1_RCC_H */
include/drivers/st/stm32mp1_pmic.h → include/drivers/st/stm32mp_pmic.h
View file @ fbf35335
/*
* Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_PMIC_H
#define STM32MP1_PMIC_H
#ifndef STM32MP_PMIC_H
#define STM32MP_PMIC_H
#include <stdbool.h>
......@@ -17,4 +17,4 @@ void initialize_pmic_i2c(void);
void initialize_pmic(void);
int pmic_ddr_power_init(enum ddr_type ddr_type);
#endif /* STM32MP1_PMIC_H */
#endif /* STM32MP_PMIC_H */
include/drivers/st/stpmu1.h → include/drivers/st/stpmic1.h
View file @ fbf35335
/*
* Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
* Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STPMU1_H
#define STPMU1_H
#ifndef STPMIC1_H
#define STPMIC1_H
#include <drivers/st/stm32_i2c.h>
#include <lib/utils_def.h>
......@@ -84,18 +84,40 @@
#define ITSOURCE2_REG 0xB1U
#define ITSOURCE3_REG 0xB2U
#define ITSOURCE4_REG 0xB3U
/* Registers masks */
#define LDO_VOLTAGE_MASK 0x7CU
#define BUCK_VOLTAGE_MASK 0xFCU
#define LDO_BUCK_VOLTAGE_SHIFT 2
#define LDO_ENABLE_MASK 0x01U
#define BUCK_ENABLE_MASK 0x01U
#define BUCK_HPLP_ENABLE_MASK 0x02U
#define LDO_HPLP_ENABLE_MASK 0x02U
#define LDO_BUCK_ENABLE_MASK 0x01U
#define LDO_BUCK_HPLP_ENABLE_MASK 0x02U
#define LDO_BUCK_HPLP_SHIFT 1
#define LDO_BUCK_RANK_MASK 0x01U
#define LDO_BUCK_RESET_MASK 0x01U
#define LDO_BUCK_PULL_DOWN_MASK 0x03U
/* Pull down register */
#define BUCK1_PULL_DOWN_SHIFT 0
#define BUCK2_PULL_DOWN_SHIFT 2
#define BUCK3_PULL_DOWN_SHIFT 4
#define BUCK4_PULL_DOWN_SHIFT 6
#define VREF_DDR_PULL_DOWN_SHIFT 4
/* Buck Mask reset register */
#define BUCK1_MASK_RESET 0
#define BUCK2_MASK_RESET 1
#define BUCK3_MASK_RESET 2
#define BUCK4_MASK_RESET 3
/* LDO Mask reset register */
#define LDO1_MASK_RESET 0
#define LDO2_MASK_RESET 1
#define LDO3_MASK_RESET 2
#define LDO4_MASK_RESET 3
#define LDO5_MASK_RESET 4
#define LDO6_MASK_RESET 5
#define VREF_DDR_MASK_RESET 6
/* Main PMIC Control Register (MAIN_CONTROL_REG) */
#define ICC_EVENT_ENABLED BIT(4)
#define PWRCTRL_POLARITY_HIGH BIT(3)
......@@ -127,14 +149,21 @@
#define SWIN_SWOUT_ENABLED BIT(2)
#define USBSW_OTG_SWITCH_ENABLED BIT(1)
int stpmu1_switch_off(void);
int stpmu1_register_read(uint8_t register_id, uint8_t *value);
int stpmu1_register_write(uint8_t register_id, uint8_t value);
int stpmu1_register_update(uint8_t register_id, uint8_t value, uint8_t mask);
int stpmu1_regulator_enable(const char *name);
int stpmu1_regulator_disable(const char *name);
uint8_t stpmu1_is_regulator_enabled(const char *name);
int stpmu1_regulator_voltage_set(const char *name, uint16_t millivolts);
void stpmu1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr);
int stpmic1_powerctrl_on(void);
int stpmic1_switch_off(void);
int stpmic1_register_read(uint8_t register_id, uint8_t *value);
int stpmic1_register_write(uint8_t register_id, uint8_t value);
int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask);
int stpmic1_regulator_enable(const char *name);
int stpmic1_regulator_disable(const char *name);
uint8_t stpmic1_is_regulator_enabled(const char *name);
int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts);
int stpmic1_regulator_voltage_get(const char *name);
int stpmic1_regulator_pull_down_set(const char *name);
int stpmic1_regulator_mask_reset_set(const char *name);
void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr);
int stpmic1_get_version(unsigned long *version);
void stpmic1_dump_regulators(void);
#endif /* STPMU1_H */
#endif /* STPMIC1_H */
include/dt-bindings/interrupt-controller/arm-gic.h 0 → 100644
View file @ fbf35335
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/*
* This header provides constants for the ARM GIC.
*/
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
/* interrupt specifier cell 0 */
#define GIC_SPI 0
#define GIC_PPI 1
#define IRQ_TYPE_NONE 0
#define IRQ_TYPE_EDGE_RISING 1
#define IRQ_TYPE_EDGE_FALLING 2
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH 4
#define IRQ_TYPE_LEVEL_LOW 8
#endif
include/dt-bindings/pinctrl/stm32-pinfunc.h
View file @ fbf35335
......@@ -32,4 +32,10 @@
#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))
/* package information */
#define STM32MP157CAA 0x1
#define STM32MP157CAB 0x2
#define STM32MP157CAC 0x4
#define STM32MP157CAD 0x8
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
plat/st/stm32mp1/bl2_io_storage.c
View file @ fbf35335
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -58,13 +58,26 @@ static const io_block_dev_spec_t mmc_block_dev_spec = {
static uintptr_t storage_dev_handle;
static const io_dev_connector_t *mmc_dev_con;
#define IMG_IDX_BL33 0
static const io_block_spec_t bl32_block_spec = {
.offset = BL32_BASE,
.length = STM32MP1_BL32_SIZE
};
static const io_block_spec_t bl2_block_spec = {
.offset = BL2_BASE,
.length = STM32MP1_BL2_SIZE,
};
static const struct stm32image_part_info bl33_partition_spec = {
.name = BL33_IMAGE_NAME,
.binary_type = BL33_BINARY_TYPE,
};
enum {
IMG_IDX_BL33,
IMG_IDX_NUM
};
static struct stm32image_device_info stm32image_dev_info_spec = {
.lba_size = MMC_BLOCK_SIZE,
.part_info[IMG_IDX_BL33] = {
......@@ -73,19 +86,12 @@ static struct stm32image_device_info stm32image_dev_info_spec = {
},
};
static io_block_spec_t stm32image_block_spec;
static const io_dev_connector_t *stm32image_dev_con;
static const io_block_spec_t bl32_block_spec = {
.offset = BL32_BASE,
.length = STM32MP1_BL32_SIZE
static io_block_spec_t stm32image_block_spec = {
.offset = 0,
.length = 0,
};
static const io_block_spec_t bl2_block_spec = {
.offset = BL2_BASE,
.length = STM32MP1_BL2_SIZE,
};
static const io_dev_connector_t *stm32image_dev_con;
static int open_dummy(const uintptr_t spec);
static int open_image(const uintptr_t spec);
......@@ -160,83 +166,18 @@ static void print_boot_device(boot_api_context_t *boot_context)
}
}
static void print_reset_reason(void)
{
uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
if (rstsr == 0U) {
WARN("Reset reason unknown\n");
return;
}
INFO("Reset reason (0x%x):\n", rstsr);
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
INFO("System exits from STANDBY\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
INFO("MPU exits from CSTANDBY\n");
return;
}
}
if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
INFO(" Power-on Reset (rst_por)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
INFO(" Brownout Reset (rst_bor)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
INFO(" System reset generated by MPU (MPSYSRST)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
INFO(" Reset due to a clock failure on HSE\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
INFO(" IWDG1 Reset (rst_iwdg1)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
INFO(" IWDG2 Reset (rst_iwdg2)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
INFO(" Pad Reset from NRST\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
INFO(" Reset due to a failure of VDD_CORE\n");
return;
}
ERROR(" Unidentified reset reason\n");
}
void stm32mp1_io_setup(void)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
struct stm32_sdmmc2_params params;
struct mmc_device_info device_info;
uintptr_t mmc_default_instance;
const partition_entry_t *entry;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
print_reset_reason();
print_boot_device(boot_context);
if ((boot_context->boot_partition_used_toboot == 1U) ||
......@@ -255,7 +196,7 @@ void stm32mp1_io_setup(void)
switch (boot_context->boot_interface_selected) {
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
dmb();
dmbsy();
memset(&params, 0, sizeof(struct stm32_sdmmc2_params));
......@@ -309,14 +250,19 @@ void stm32mp1_io_setup(void)
stm32image_dev_info_spec.device_size =
stm32_sdmmc2_mmc_get_device_size();
stm32image_dev_info_spec.part_info[IMG_IDX_BL33].part_offset =
get_partition_entry(BL33_IMAGE_NAME)->start;
stm32image_dev_info_spec.part_info[IMG_IDX_BL33].bkp_offset =
get_partition_entry(BL33_IMAGE_NAME)->length;
stm32image_block_spec.offset = 0;
stm32image_block_spec.length =
get_partition_entry(BL33_IMAGE_NAME)->length;
for (idx = 0U; idx < IMG_IDX_NUM; idx++) {
part = &stm32image_dev_info_spec.part_info[idx];
entry = get_partition_entry(part->name);
if (entry == NULL) {
ERROR("Partition %s not found\n",
part->name);
panic();
}
part->part_offset = entry->start;
part->bkp_offset = 0U;
}
/*
* Re-open MMC with io_mmc, for better perfs compared to
......
plat/st/stm32mp1/bl2_plat_setup.c
View file @ fbf35335
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -16,8 +16,8 @@
#include <drivers/delay_timer.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/st/stm32_console.h>
#include <drivers/st/stm32mp_pmic.h>
#include <drivers/st/stm32mp1_clk.h>
#include <drivers/st/stm32mp1_pmic.h>
#include <drivers/st/stm32mp1_pwr.h>
#include <drivers/st/stm32mp1_ram.h>
#include <drivers/st/stm32mp1_rcc.h>
......@@ -33,8 +33,95 @@
static struct console_stm32 console;
void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
static void print_reset_reason(void)
{
uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
if (rstsr == 0U) {
WARN("Reset reason unknown\n");
return;
}
INFO("Reset reason (0x%x):\n", rstsr);
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
INFO("System exits from STANDBY\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
INFO("MPU exits from CSTANDBY\n");
return;
}
}
if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
INFO(" Power-on Reset (rst_por)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
INFO(" Brownout Reset (rst_bor)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
INFO(" System reset generated by MCU (MCSYSRST)\n");
} else {
INFO(" Local reset generated by MCU (MCSYSRST)\n");
}
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
INFO(" System reset generated by MPU (MPSYSRST)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
INFO(" Reset due to a clock failure on HSE\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
INFO(" IWDG1 Reset (rst_iwdg1)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
INFO(" IWDG2 Reset (rst_iwdg2)\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
INFO(" MPU Processor 0 Reset\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
INFO(" MPU Processor 1 Reset\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
INFO(" Pad Reset from NRST\n");
return;
}
if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
INFO(" Reset due to a failure of VDD_CORE\n");
return;
}
ERROR(" Unidentified reset reason\n");
}
void bl2_el3_early_platform_setup(u_register_t arg0,
u_register_t arg1 __unused,
u_register_t arg2 __unused,
u_register_t arg3 __unused)
{
stm32mp1_save_boot_ctx_address(arg0);
}
......@@ -59,12 +146,38 @@ void bl2_platform_setup(void)
void bl2_el3_plat_arch_setup(void)
{
int32_t result;
struct dt_node_info dt_dev_info;
struct dt_node_info dt_uart_info;
const char *board_model;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
uint32_t clk_rate;
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE);
/* Prevent corruption of preloaded BL32 */
mmap_add_region(BL32_BASE, BL32_BASE,
BL32_LIMIT - BL32_BASE,
MT_MEMORY | MT_RO | MT_SECURE);
/* Map non secure DDR for BL33 load and DDR training area restore */
mmap_add_region(STM32MP1_DDR_BASE,
STM32MP1_DDR_BASE,
STM32MP1_DDR_MAX_SIZE,
MT_MEMORY | MT_RW | MT_NS);
/* Prevent corruption of preloaded Device Tree */
mmap_add_region(DTB_BASE, DTB_BASE,
DTB_LIMIT - DTB_BASE,
MT_MEMORY | MT_RO | MT_SECURE);
configure_mmu();
if (dt_open_and_check() < 0) {
panic();
}
/*
* Disable the backup domain write protection.
* The protection is enable at each reset by hardware
......@@ -88,28 +201,8 @@ void bl2_el3_plat_arch_setup(void)
mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST);
}
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE);
/* Prevent corruption of preloaded BL32 */
mmap_add_region(BL32_BASE, BL32_BASE,
BL32_LIMIT - BL32_BASE,
MT_MEMORY | MT_RO | MT_SECURE);
/* Prevent corruption of preloaded Device Tree */
mmap_add_region(DTB_BASE, DTB_BASE,
DTB_LIMIT - DTB_BASE,
MT_MEMORY | MT_RO | MT_SECURE);
configure_mmu();
generic_delay_timer_init();
if (dt_open_and_check() < 0) {
panic();
}
if (stm32mp1_clk_probe() < 0) {
panic();
}
......@@ -118,12 +211,12 @@ void bl2_el3_plat_arch_setup(void)
panic();
}
result = dt_get_stdout_uart_info(&dt_dev_info);
result = dt_get_stdout_uart_info(&dt_uart_info);
if ((result <= 0) ||
(dt_dev_info.status == 0U) ||
(dt_dev_info.clock < 0) ||
(dt_dev_info.reset < 0)) {
(dt_uart_info.status == 0U) ||
(dt_uart_info.clock < 0) ||
(dt_uart_info.reset < 0)) {
goto skip_console_init;
}
......@@ -131,25 +224,25 @@ void bl2_el3_plat_arch_setup(void)
goto skip_console_init;
}
if (stm32mp1_clk_enable((unsigned long)dt_dev_info.clock) != 0) {
if (stm32mp1_clk_enable((unsigned long)dt_uart_info.clock) != 0) {
goto skip_console_init;
}
stm32mp1_reset_assert((uint32_t)dt_dev_info.reset);
stm32mp1_reset_assert((uint32_t)dt_uart_info.reset);
udelay(2);
stm32mp1_reset_deassert((uint32_t)dt_dev_info.reset);
stm32mp1_reset_deassert((uint32_t)dt_uart_info.reset);
mdelay(1);
clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_dev_info.clock);
clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_uart_info.clock);
if (console_stm32_register(dt_dev_info.base, clk_rate,
if (console_stm32_register(dt_uart_info.base, clk_rate,
STM32MP1_UART_BAUDRATE, &console) == 0) {
panic();
}
board_model = dt_get_board_model();
if (board_model != NULL) {
NOTICE("%s\n", board_model);
NOTICE("Model: %s\n", board_model);
}
skip_console_init:
......@@ -162,5 +255,7 @@ skip_console_init:
stm32mp1_arch_security_setup();
print_reset_reason();
stm32mp1_io_setup();
}
plat/st/stm32mp1/include/platform_def.h
View file @ fbf35335
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -30,8 +30,8 @@
#define BL33_BINARY_TYPE U(0x0)
#define STM32MP1_PRIMARY_CPU U(0x0)
#define STM32MP1_SECONDARY_CPU U(0x1)
#define PLATFORM_CACHE_LINE_SIZE 64
#define PLATFORM_CLUSTER_COUNT ULL(1)
#define PLATFORM_CLUSTER0_CORE_COUNT U(2)
#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
......@@ -39,9 +39,9 @@
PLATFORM_CLUSTER0_CORE_COUNT)
#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
#define MAX_IO_DEVICES 4
#define MAX_IO_HANDLES 4
#define MAX_IO_BLOCK_DEVICES 1
#define MAX_IO_DEVICES U(4)
#define MAX_IO_HANDLES U(4)
#define MAX_IO_BLOCK_DEVICES U(1)
/*******************************************************************************
* BL2 specific defines.
......@@ -81,8 +81,8 @@
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is
......@@ -123,9 +123,6 @@
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \
GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(STM32MP1_IRQ_TAMPSERRS, \
GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(STM32MP1_IRQ_AXIERRIRQ, \
GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_LEVEL), \
......
plat/st/stm32mp1/include/stm32mp1_dt.h
View file @ fbf35335
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -9,12 +9,16 @@
#include <stdbool.h>
#define DT_DISABLED U(0)
#define DT_NON_SECURE U(1)
#define DT_SECURE U(2)
#define DT_SHARED (DT_NON_SECURE | DT_SECURE)
struct dt_node_info {
uint32_t base;
int32_t clock;
int32_t reset;
bool status;
bool sec_status;
uint32_t status;
};
/*******************************************************************************
......@@ -23,13 +27,11 @@ struct dt_node_info {
int dt_open_and_check(void);
int fdt_get_address(void **fdt_addr);
bool fdt_check_node(int node);
bool fdt_check_status(int node);
bool fdt_check_secure_status(int node);
uint32_t fdt_get_status(int node);
uint32_t fdt_read_uint32_default(int node, const char *prop_name,
uint32_t dflt_value);
int fdt_read_uint32_array(int node, const char *prop_name,
uint32_t *array, uint32_t count);
int dt_set_pinctrl_config(int node);
int dt_set_stdout_pinctrl(void);
void dt_fill_device_info(struct dt_node_info *info, int node);
int dt_get_node(struct dt_node_info *info, int offset, const char *compat);
......
plat/st/stm32mp1/include/stm32mp1_private.h
View file @ fbf35335
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -21,4 +21,8 @@ uintptr_t stm32mp1_get_boot_ctx_address(void);
void stm32mp1_gic_pcpu_init(void);
void stm32mp1_gic_init(void);
uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
#endif /* STM32MP1_PRIVATE_H */
plat/st/stm32mp1/include/stm32mp1_smc.h 0 → 100644
View file @ fbf35335
/*
* Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_SMC_H
#define STM32MP1_SMC_H
/*
* SMC function IDs for STM32 Service queries
* STM32 SMC services use the space between 0x82000000 and 0x8200FFFF
* like this is defined in SMC calling Convention by ARM
* for SiP (silicon Partner)
* https://developer.arm.com/docs/den0028/latest
*/
/* Secure Service access from Non-secure */
/*
* STM32_SMC_BSEC call API
*
* Argument a0: (input) SMCC ID
* (output) status return code
* Argument a1: (input) Service ID (STM32_SMC_BSEC_xxx)
* Argument a2: (input) OTP index
* (output) OTP read value, if applicable
* Argument a3: (input) OTP value if applicable
*/
#define STM32_SMC_BSEC 0x82001003
/* SMC function IDs for SiP Service queries */
#define STM32_SIP_SVC_CALL_COUNT 0x8200ff00
#define STM32_SIP_SVC_UID 0x8200ff01
/* 0x8200ff02 is reserved */
#define STM32_SIP_SVC_VERSION 0x8200ff03
/* STM32 SiP Service Calls version numbers */
#define STM32_SIP_SVC_VERSION_MAJOR 0x0
#define STM32_SIP_SVC_VERSION_MINOR 0x1
/* Number of STM32 SiP Calls implemented */
#define STM32_COMMON_SIP_NUM_CALLS 4
/* Service for BSEC */
#define STM32_SMC_READ_SHADOW 0x01
#define STM32_SMC_PROG_OTP 0x02
#define STM32_SMC_WRITE_SHADOW 0x03
#define STM32_SMC_READ_OTP 0x04
#endif /* STM32MP1_SMC_H */
plat/st/stm32mp1/platform.mk
View file @ fbf35335
This diff is collapsed.
plat/st/stm32mp1/services/bsec_svc.c 0 → 100644
View file @ fbf35335
This diff is collapsed.
plat/st/stm32mp1/services/bsec_svc.h 0 → 100644
View file @ fbf35335
This diff is collapsed.
plat/st/stm32mp1/services/stm32mp1_svc_setup.c 0 → 100644
View file @ fbf35335
This diff is collapsed.
plat/st/stm32mp1/sp_min/sp_min-stm32mp1.mk
View file @ fbf35335
#
# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
......@@ -19,3 +19,7 @@ BL32_SOURCES += drivers/arm/gic/common/gic_common.c \
# Generic PSCI
BL32_SOURCES += plat/common/plat_psci_common.c
# stm32mp1 specific services
BL32_SOURCES += plat/st/stm32mp1/services/bsec_svc.c \
plat/st/stm32mp1/services/stm32mp1_svc_setup.c
plat/st/stm32mp1/sp_min/sp_min_setup.c
View file @ fbf35335
This diff is collapsed.
plat/st/stm32mp1/stm32mp1_common.c
View file @ fbf35335
This diff is collapsed.
plat/st/stm32mp1/stm32mp1_def.h
View file @ fbf35335
This diff is collapsed.
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