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Commit fc037ffc authored by Madhukar Pappireddy's avatar Madhukar Pappireddy Committed by TrustedFirmware Code Review
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Merge changes Id2b1822c,Ia9a563a1,I11f65d49,If9318a51,I46801b56, ... into integration 

* changes:
  drivers: renesas: Move plat common sources
  plat: renesas: Move headers and assembly files to common folder
  plat: renesas: rcar: include: Code cleanup
  plat: renesas:rcar: Fix checkpatch warnings
  plat: renesas: rcar: Fix checkpatch warnings
  plat: renesas:rcar: Code cleanup
  plat: renesas: rcar: Fix coding style
parents 88e33b0c be92e5a2
Hide whitespace changes
Inline Side-by-side
plat/renesas/common/common.mk 0 → 100644
View file @ fc037ffc
#
# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
PROGRAMMABLE_RESET_ADDRESS := 0
COLD_BOOT_SINGLE_CPU := 1
ARM_CCI_PRODUCT_ID := 500
TRUSTED_BOARD_BOOT := 1
RESET_TO_BL31 := 1
GENERATE_COT := 1
BL2_AT_EL3 := 1
ENABLE_SVE_FOR_NS := 0
MULTI_CONSOLE_API := 1
CRASH_REPORTING := 1
HANDLE_EA_EL3_FIRST := 1
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
ifeq (${SPD},none)
SPD_NONE:=1
$(eval $(call add_define,SPD_NONE))
endif
# LSI setting common define
RCAR_H3:=0
RCAR_M3:=1
RCAR_M3N:=2
RCAR_E3:=3
RCAR_H3N:=4
RCAR_D3:=5
RCAR_V3M:=6
RCAR_AUTO:=99
$(eval $(call add_define,RCAR_H3))
$(eval $(call add_define,RCAR_M3))
$(eval $(call add_define,RCAR_M3N))
$(eval $(call add_define,RCAR_E3))
$(eval $(call add_define,RCAR_H3N))
$(eval $(call add_define,RCAR_D3))
$(eval $(call add_define,RCAR_V3M))
$(eval $(call add_define,RCAR_AUTO))
RCAR_CUT_10:=0
RCAR_CUT_11:=1
RCAR_CUT_13:=3
RCAR_CUT_20:=10
RCAR_CUT_30:=20
$(eval $(call add_define,RCAR_CUT_10))
$(eval $(call add_define,RCAR_CUT_11))
$(eval $(call add_define,RCAR_CUT_13))
$(eval $(call add_define,RCAR_CUT_20))
$(eval $(call add_define,RCAR_CUT_30))
# Enable workarounds for selected Cortex-A53 erratas.
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
# Enable workarounds for selected Cortex-A57 erratas.
ERRATA_A57_859972 := 1
ERRATA_A57_813419 := 1
PLAT_INCLUDES := -Iplat/renesas/common/include/registers \
-Iplat/renesas/common/include \
-Iplat/renesas/common
PLAT_BL_COMMON_SOURCES := drivers/renesas/common/iic_dvfs/iic_dvfs.c \
plat/renesas/common/rcar_common.c
RCAR_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c
BL2_SOURCES += ${RCAR_GIC_SOURCES} \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
${LIBFDT_SRCS} \
common/desc_image_load.c \
drivers/renesas/common/common.c \
drivers/io/io_storage.c
BL31_SOURCES += ${RCAR_GIC_SOURCES} \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
plat/common/plat_psci_common.c \
drivers/renesas/common/common.c \
drivers/arm/cci/cci.c
include lib/xlat_tables_v2/xlat_tables.mk
include drivers/auth/mbedtls/mbedtls_crypto.mk
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
plat/renesas/rcar/include/platform_def.h → plat/renesas/common/include/platform_def.h
View file @ fc037ffc
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -29,20 +29,20 @@
/* Size of cacheable stacks */
#if IMAGE_BL1
#if TRUSTED_BOARD_BOOT
#define PLATFORM_STACK_SIZE U(0x1000)
#define PLATFORM_STACK_SIZE U(0x1000)
#else
#define PLATFORM_STACK_SIZE U(0x440)
#define PLATFORM_STACK_SIZE U(0x440)
#endif
#elif IMAGE_BL2
#if TRUSTED_BOARD_BOOT
#define PLATFORM_STACK_SIZE U(0x1000)
#define PLATFORM_STACK_SIZE U(0x1000)
#else
#define PLATFORM_STACK_SIZE U(0x400)
#define PLATFORM_STACK_SIZE U(0x400)
#endif
#elif IMAGE_BL31
#define PLATFORM_STACK_SIZE U(0x400)
#define PLATFORM_STACK_SIZE U(0x400)
#elif IMAGE_BL32
#define PLATFORM_STACK_SIZE U(0x440)
#define PLATFORM_STACK_SIZE U(0x440)
#endif
#define BL332_IMAGE_ID (NS_BL2U_IMAGE_ID + 1)
......@@ -97,11 +97,13 @@
#define MAX_IO_DEVICES U(3)
#define MAX_IO_HANDLES U(4)
/*******************************************************************************
/*
******************************************************************************
* BL2 specific defines.
******************************************************************************/
/* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth. */
******************************************************************************
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth.
*/
#define RCAR_SYSRAM_BASE U(0xE6300000)
#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
#define BL2_LIMIT U(0xE6320000)
......@@ -121,17 +123,19 @@
#endif
#define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
/*******************************************************************************
/*
******************************************************************************
* BL31 specific defines.
******************************************************************************/
/* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL3-1 debug size plus a little space for growth. */
******************************************************************************
* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL3-1 debug size plus a little space for growth.
*/
#define BL31_BASE (RCAR_TRUSTED_SRAM_BASE)
#define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE + \
RCAR_TRUSTED_SRAM_SIZE)
#define RCAR_BL31_LOG_BASE (0x44040000)
#define RCAR_BL31_SDRAM_BTM (RCAR_BL31_LOG_BASE + 0x14000)
#define RCAR_BL31_LOG_SIZE (RCAR_BL31_SDRAM_BTM - RCAR_BL31_LOG_BASE)
#define RCAR_BL31_LOG_BASE (0x44040000)
#define RCAR_BL31_SDRAM_BTM (RCAR_BL31_LOG_BASE + 0x14000)
#define RCAR_BL31_LOG_SIZE (RCAR_BL31_SDRAM_BTM - RCAR_BL31_LOG_BASE)
#define BL31_SRAM_BASE (DEVICE_SRAM_BASE)
#define BL31_SRAM_LIMIT (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
......@@ -176,7 +180,7 @@
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
* caches. Such alignment ensures that two mailboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
......
plat/renesas/rcar/include/rcar_def.h → plat/renesas/common/include/rcar_def.h
View file @ fc037ffc
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -33,13 +33,13 @@
#define DRAM1_SIZE U(0x80000000)
#define DRAM1_NS_BASE (DRAM1_BASE + U(0x10000000))
#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_NS_BASE)
#define DRAM_40BIT_BASE ULL(0x0400000000)
#define DRAM_40BIT_SIZE ULL(0x0400000000)
#define DRAM_PROTECTED_BASE ULL(0x43F00000)
#define DRAM_40BIT_PROTECTED_BASE ULL(0x0403F00000)
#define DRAM_PROTECTED_SIZE ULL(0x03F00000)
#define RCAR_BL31_CRASH_BASE U(0x4403F000)
#define RCAR_BL31_CRASH_SIZE U(0x00001000)
#define DRAM_40BIT_BASE ULL(0x0400000000)
#define DRAM_40BIT_SIZE ULL(0x0400000000)
#define DRAM_PROTECTED_BASE ULL(0x43F00000)
#define DRAM_40BIT_PROTECTED_BASE ULL(0x0403F00000)
#define DRAM_PROTECTED_SIZE ULL(0x03F00000)
#define RCAR_BL31_CRASH_BASE U(0x4403F000)
#define RCAR_BL31_CRASH_SIZE U(0x00001000)
/* Entrypoint mailboxes */
#define MBOX_BASE RCAR_SHARED_MEM_BASE
#define MBOX_SIZE 0x200
......@@ -47,15 +47,19 @@
#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
#define BOOT_KIND_BASE (RCAR_SHARED_MEM_BASE + \
RCAR_SHARED_MEM_SIZE - 0x100)
/* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU */
/*
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU
*/
#if USE_COHERENT_MEM
#define RCAR_BL_REGIONS (3)
#else
#define RCAR_BL_REGIONS (2)
#endif
/* The RCAR_MAX_MMAP_REGIONS depend on the number of entries in rcar_mmap[]
* defined for each BL stage in rcar_common.c. */
/*
* The RCAR_MAX_MMAP_REGIONS depends on the number of entries in rcar_mmap[]
* defined for each BL stage in rcar_common.c.
*/
#if IMAGE_BL2
#define RCAR_MMAP_ENTRIES (9)
#endif
......@@ -73,24 +77,24 @@
/* BL33 */
#define NS_IMAGE_OFFSET (DRAM1_BASE + U(0x09000000))
/* BL31 */
#define RCAR_DEVICE_BASE DEVICE_RCAR_BASE
#define RCAR_DEVICE_SIZE (0x1A000000)
#define RCAR_LOG_RES_SIZE (512/8)
#define RCAR_LOG_HEADER_SIZE (16)
#define RCAR_LOG_OTHER_SIZE (RCAR_LOG_HEADER_SIZE + \
#define RCAR_DEVICE_BASE DEVICE_RCAR_BASE
#define RCAR_DEVICE_SIZE (0x1A000000)
#define RCAR_LOG_RES_SIZE (64)
#define RCAR_LOG_HEADER_SIZE (16)
#define RCAR_LOG_OTHER_SIZE (RCAR_LOG_HEADER_SIZE + \
RCAR_LOG_RES_SIZE)
#define RCAR_BL31_LOG_MAX (RCAR_BL31_LOG_SIZE - \
#define RCAR_BL31_LOG_MAX (RCAR_BL31_LOG_SIZE - \
RCAR_LOG_OTHER_SIZE)
#define RCAR_CRASH_STACK RCAR_BL31_CRASH_BASE
#define AARCH64_SPACE_BASE ULL(0x00000000000)
#define AARCH64_SPACE_SIZE ULL(0x10000000000)
#define RCAR_CRASH_STACK RCAR_BL31_CRASH_BASE
#define AARCH64_SPACE_BASE ULL(0x00000000000)
#define AARCH64_SPACE_SIZE ULL(0x10000000000)
/* CCI related constants */
#define CCI500_BASE U(0xF1200000)
#define CCI500_CLUSTER0_SL_IFACE_IX (2)
#define CCI500_CLUSTER1_SL_IFACE_IX (3)
#define CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3 (1)
#define CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3 (2)
#define RCAR_CCI_BASE CCI500_BASE
#define RCAR_CCI_BASE CCI500_BASE
/* GIC */
#define RCAR_GICD_BASE U(0xF1010000)
#define RCAR_GICR_BASE U(0xF1010000)
......@@ -106,47 +110,47 @@
#define ARM_IRQ_SEC_SGI_5 U(13)
#define ARM_IRQ_SEC_SGI_6 U(14)
#define ARM_IRQ_SEC_SGI_7 U(15)
#define ARM_IRQ_SEC_RPC U(70)
#define ARM_IRQ_SEC_TIMER U(166)
#define ARM_IRQ_SEC_TIMER_UP U(171)
#define ARM_IRQ_SEC_WDT U(173)
#define ARM_IRQ_SEC_CRYPT U(102)
#define ARM_IRQ_SEC_CRYPT_SecPKA U(97)
#define ARM_IRQ_SEC_CRYPT_PubPKA U(98)
#define ARM_IRQ_SEC_RPC U(70)
#define ARM_IRQ_SEC_TIMER U(166)
#define ARM_IRQ_SEC_TIMER_UP U(171)
#define ARM_IRQ_SEC_WDT U(173)
#define ARM_IRQ_SEC_CRYPT U(102)
#define ARM_IRQ_SEC_CRYPT_SecPKA U(97)
#define ARM_IRQ_SEC_CRYPT_PubPKA U(98)
/* Timer control */
#define RCAR_CNTC_BASE U(0xE6080000)
#define RCAR_CNTC_BASE U(0xE6080000)
/* Reset */
#define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */
#define RCAR_MODEMR U(0xE6160060) /* Mode pin */
#define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */
#define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */
#define RCAR_SRESCR U(0xE6160110) /* Soft Power On Reset */
#define RCAR_CA53WUPCR U(0xE6151010) /* Wake-up control A53 */
#define RCAR_CA57WUPCR U(0xE6152010) /* Wake-up control A57 */
#define RCAR_CA53PSTR U(0xE6151040) /* Power status A53 */
#define RCAR_CA57PSTR U(0xE6152040) /* Power status A57 */
#define RCAR_CA53CPU0CR U(0xE6151100) /* CPU control A53 */
#define RCAR_CA57CPU0CR U(0xE6152100) /* CPU control A57 */
#define RCAR_CA53CPUCMCR U(0xE6151184) /* Common power A53 */
#define RCAR_CA57CPUCMCR U(0xE6152184) /* Common power A57 */
#define RCAR_WUPMSKCA57 U(0xE6180014) /* Wake-up mask A57 */
#define RCAR_WUPMSKCA53 U(0xE6180018) /* Wake-up mask A53 */
#define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */
#define RCAR_MODEMR U(0xE6160060) /* Mode pin */
#define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */
#define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */
#define RCAR_SRESCR U(0xE6160110) /* Soft Power On Reset */
#define RCAR_CA53WUPCR U(0xE6151010) /* Wake-up control A53 */
#define RCAR_CA57WUPCR U(0xE6152010) /* Wake-up control A57 */
#define RCAR_CA53PSTR U(0xE6151040) /* Power status A53 */
#define RCAR_CA57PSTR U(0xE6152040) /* Power status A57 */
#define RCAR_CA53CPU0CR U(0xE6151100) /* CPU control A53 */
#define RCAR_CA57CPU0CR U(0xE6152100) /* CPU control A57 */
#define RCAR_CA53CPUCMCR U(0xE6151184) /* Common power A53 */
#define RCAR_CA57CPUCMCR U(0xE6152184) /* Common power A57 */
#define RCAR_WUPMSKCA57 U(0xE6180014) /* Wake-up mask A57 */
#define RCAR_WUPMSKCA53 U(0xE6180018) /* Wake-up mask A53 */
/* SYSC */
#define RCAR_PWRSR3 U(0xE6180140) /* Power stat A53-SCU */
#define RCAR_PWRSR5 U(0xE61801C0) /* Power stat A57-SCU */
#define RCAR_SYSCIER U(0xE618000C) /* Interrupt enable */
#define RCAR_SYSCIMR U(0xE6180010) /* Interrupt mask */
#define RCAR_SYSCSR U(0xE6180000) /* SYSC status */
#define RCAR_PWRONCR3 U(0xE618014C) /* Power resume A53-SCU */
#define RCAR_PWRONCR5 U(0xE61801CC) /* Power resume A57-SCU */
#define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutof A53-SCU */
#define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutof A57-SCU */
#define RCAR_PWRER3 U(0xE6180154) /* shutoff/resume error */
#define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */
#define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */
#define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */
#define RCAR_PWRSR3 U(0xE6180140) /* Power stat A53-SCU */
#define RCAR_PWRSR5 U(0xE61801C0) /* Power stat A57-SCU */
#define RCAR_SYSCIER U(0xE618000C) /* Interrupt enable */
#define RCAR_SYSCIMR U(0xE6180010) /* Interrupt mask */
#define RCAR_SYSCSR U(0xE6180000) /* SYSC status */
#define RCAR_PWRONCR3 U(0xE618014C) /* Power resume A53-SCU */
#define RCAR_PWRONCR5 U(0xE61801CC) /* Power resume A57-SCU */
#define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutoff A53-SCU */
#define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutoff A57-SCU */
#define RCAR_PWRER3 U(0xE6180154) /* shutoff/resume error */
#define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */
#define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */
#define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */
/* Product register */
#define RCAR_PRR U(0xFFF00044)
#define RCAR_PRR U(0xFFF00044)
#define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */
#define RCAR_MAJOR_MASK U(0x000000F0)
#define RCAR_MINOR_MASK U(0x0000000F)
......@@ -198,39 +202,39 @@
/* Memory mapped Generic timer interfaces */
#define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE
/* MODEMR PLL masks and bitfield values */
#define CHECK_MD13_MD14 U(0x6000)
#define MD14_MD13_TYPE_0 U(0x0000) /* MD14=0 MD13=0 */
#define MD14_MD13_TYPE_1 U(0x2000) /* MD14=0 MD13=1 */
#define MD14_MD13_TYPE_2 U(0x4000) /* MD14=1 MD13=0 */
#define MD14_MD13_TYPE_3 U(0x6000) /* MD14=1 MD13=1 */
#define CHECK_MD13_MD14 U(0x6000)
#define MD14_MD13_TYPE_0 U(0x0000) /* MD14=0 MD13=0 */
#define MD14_MD13_TYPE_1 U(0x2000) /* MD14=0 MD13=1 */
#define MD14_MD13_TYPE_2 U(0x4000) /* MD14=1 MD13=0 */
#define MD14_MD13_TYPE_3 U(0x6000) /* MD14=1 MD13=1 */
/* Frequency of EXTAL(Hz) */
#define EXTAL_MD14_MD13_TYPE_0 U(8333300) /* MD14=0 MD13=0 */
#define EXTAL_MD14_MD13_TYPE_1 U(10000000) /* MD14=0 MD13=1 */
#define EXTAL_MD14_MD13_TYPE_2 U(12500000) /* MD14=1 MD13=0 */
#define EXTAL_MD14_MD13_TYPE_3 U(16666600) /* MD14=1 MD13=1 */
#define EXTAL_SALVATOR_XS U(8320000) /* Salvator-XS */
#define EXTAL_MD14_MD13_TYPE_0 U(8333300) /* MD14=0 MD13=0 */
#define EXTAL_MD14_MD13_TYPE_1 U(10000000) /* MD14=0 MD13=1 */
#define EXTAL_MD14_MD13_TYPE_2 U(12500000) /* MD14=1 MD13=0 */
#define EXTAL_MD14_MD13_TYPE_3 U(16666600) /* MD14=1 MD13=1 */
#define EXTAL_SALVATOR_XS U(8320000) /* Salvator-XS */
#define EXTAL_EBISU U(24000000) /* Ebisu */
#define EXTAL_DRAAK U(24000000) /* Draak */
/* CPG write protect registers */
#define CPGWPR_PASSWORD (0x5A5AFFFFU)
#define CPGWPCR_PASSWORD (0xA5A50000U)
/* CPG write protect registers */
#define CPGWPR_PASSWORD (0x5A5AFFFFU)
#define CPGWPCR_PASSWORD (0xA5A50000U)
/* CA5x Debug Resource control registers */
#define CPG_CA57DBGRCR (CPG_BASE + 0x2180U)
#define CPG_CA53DBGRCR (CPG_BASE + 0x1180U)
#define DBGCPUPREN ((uint32_t)1U << 19U)
#define CPG_PLL0CR (CPG_BASE + 0x00D8U)
#define CPG_PLL2CR (CPG_BASE + 0x002CU)
#define CPG_PLL4CR (CPG_BASE + 0x01F4U)
#define CPG_CA57DBGRCR (CPG_BASE + 0x2180U)
#define CPG_CA53DBGRCR (CPG_BASE + 0x1180U)
#define DBGCPUPREN ((uint32_t)1U << 19U)
#define CPG_PLL0CR (CPG_BASE + 0x00D8U)
#define CPG_PLL2CR (CPG_BASE + 0x002CU)
#define CPG_PLL4CR (CPG_BASE + 0x01F4U)
#define CPG_CPGWPCR (CPG_BASE + 0x0904U)
/* RST Registers */
#define RST_BASE (0xE6160000U)
#define RST_WDTRSTCR (RST_BASE + 0x0054U)
#define RST_BASE (0xE6160000U)
#define RST_WDTRSTCR (RST_BASE + 0x0054U)
#define RST_MODEMR (RST_BASE + 0x0060U)
#define WDTRSTCR_PASSWORD (0xA55A0000U)
#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)
#define WDTRSTCR_PASSWORD (0xA55A0000U)
#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U)
/* MFIS Registers */
#define MFISWPCNTR_PASSWORD (0xACCE0000U)
#define MFISWPCNTR (0xE6260900U)
#define MFISWPCNTR_PASSWORD (0xACCE0000U)
#define MFISWPCNTR (0xE6260900U)
/* IPMMU registers */
#define IPMMU_MM_BASE (0xE67B0000U)
#define IPMMUMM_IMSCTLR (IPMMU_MM_BASE + 0x0500U)
......@@ -263,8 +267,8 @@
#define IPMMU_DS1_BASE (0xE7740000U)
#define IPMMUDS1_IMSCTLR (IPMMU_DS1_BASE + 0x0500U)
/* ARMREG registers */
#define P_ARMREG_SEC_CTRL (0xE62711F0U)
#define P_ARMREG_SEC_CTRL_PROT (0x00000001U)
#define P_ARMREG_SEC_CTRL (0xE62711F0U)
#define P_ARMREG_SEC_CTRL_PROT (0x00000001U)
/* MIDR */
#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
......@@ -279,28 +283,28 @@
#define RCAR_COLD_BOOT (0x00U)
#define RCAR_WARM_BOOT (0x01U)
#if PMIC_ROHM_BD9571 && RCAR_SYSTEM_RESET_KEEPON_DDR
#define KEEP10_MAGIC (0x55U)
#define KEEP10_MAGIC (0x55U)
#endif
/* lossy registers */
#define LOSSY_PARAMS_BASE (0x47FD7000U)
#define AXI_DCMPAREACRA0 (0xE6784100U)
#define AXI_DCMPAREACRB0 (0xE6784104U)
#define LOSSY_PARAMS_BASE (0x47FD7000U)
#define AXI_DCMPAREACRA0 (0xE6784100U)
#define AXI_DCMPAREACRB0 (0xE6784104U)
#define LOSSY_ENABLE (0x80000000U)
#define LOSSY_DISABLE (0x00000000U)
#define LOSSY_FMT_YUVPLANAR (0x00000000U)
#define LOSSY_FMT_YUV422INTLV (0x20000000U)
#define LOSSY_FMT_ARGB8888 (0x40000000U)
#define LOSSY_ST_ADDR0 (0x54000000U)
#define LOSSY_END_ADDR0 (0x57000000U)
#define LOSSY_FMT0 LOSSY_FMT_YUVPLANAR
#define LOSSY_ENA_DIS0 LOSSY_ENABLE
#define LOSSY_ST_ADDR1 0x0U
#define LOSSY_END_ADDR1 0x0U
#define LOSSY_FMT1 LOSSY_FMT_ARGB8888
#define LOSSY_ENA_DIS1 LOSSY_DISABLE
#define LOSSY_ST_ADDR2 0x0U
#define LOSSY_END_ADDR2 0x0U
#define LOSSY_FMT2 LOSSY_FMT_YUV422INTLV
#define LOSSY_ENA_DIS2 LOSSY_DISABLE
#define LOSSY_ST_ADDR0 (0x54000000U)
#define LOSSY_END_ADDR0 (0x57000000U)
#define LOSSY_FMT0 LOSSY_FMT_YUVPLANAR
#define LOSSY_ENA_DIS0 LOSSY_ENABLE
#define LOSSY_ST_ADDR1 0x0U
#define LOSSY_END_ADDR1 0x0U
#define LOSSY_FMT1 LOSSY_FMT_ARGB8888
#define LOSSY_ENA_DIS1 LOSSY_DISABLE
#define LOSSY_ST_ADDR2 0x0U
#define LOSSY_END_ADDR2 0x0U
#define LOSSY_FMT2 LOSSY_FMT_YUV422INTLV
#define LOSSY_ENA_DIS2 LOSSY_DISABLE
#endif /* RCAR_DEF_H */
plat/renesas/rcar/include/rcar_private.h → plat/renesas/common/include/rcar_private.h
View file @ fc037ffc
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -7,12 +7,12 @@
#ifndef RCAR_PRIVATE_H
#define RCAR_PRIVATE_H
#include <platform_def.h>
#include <common/bl_common.h>
#include <lib/bakery_lock.h>
#include <lib/el3_runtime/cpu_data.h>
#include <platform_def.h>
typedef volatile struct mailbox {
unsigned long value __aligned(CACHE_WRITEBACK_GRANULE);
} mailbox_t;
......@@ -62,17 +62,18 @@ typedef struct rcar_cpu_data {
*/
#define rcar_lock_init(_lock_arg)
#define rcar_lock_get(_lock_arg) \
bakery_lock_get(_lock_arg, \
#define rcar_lock_get(_lock_arg) \
bakery_lock_get(_lock_arg, \
CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET)
#define rcar_lock_release(_lock_arg) \
bakery_lock_release(_lock_arg, \
bakery_lock_release(_lock_arg, \
CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET)
/* Ensure that the size of the RCAR specific per-cpu data structure and the size
/*
* Ensure that the size of the RCAR specific per-cpu data structure and the size
* of the memory allocated in generic per-cpu data for the platform are the same
*/
CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(rcar_cpu_data_t),
CASSERT(sizeof(rcar_cpu_data_t) == PLAT_PCPU_DATA_SIZE,
rcar_pcpu_data_size_mismatch);
#endif
/*
......@@ -84,7 +85,7 @@ void rcar_configure_mmu_el3(unsigned long total_base,
#if USE_COHERENT_MEM
, unsigned long coh_start, unsigned long coh_limit
#endif
);
);
void rcar_setup_topology(void);
void rcar_cci_disable(void);
......
plat/renesas/common/include/registers/lifec_registers.h 0 → 100644
View file @ fc037ffc
/*
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef LIFEC_REGISTERS_H
#define LIFEC_REGISTERS_H
#define LIFEC_SEC_BASE (0xE6110000U)
#define SEC_SRC (LIFEC_SEC_BASE + 0x0008U)
#define SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U)
#define SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U)
#define SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U)
#define SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU)
#define SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U)
#define SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU)
#define SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U)
#define SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U)
#define SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U)
#define SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU)
#define SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U)
#define SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U)
#define SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U)
#define SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU)
#define SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U)
#define SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U)
#define SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U)
#define SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU)
#define SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U)
#define SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U)
#define SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U)
#define SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU)
#define SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U)
#define SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U)
#define SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U)
#define SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU)
#define SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U)
#define SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U)
#define SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U)
#define SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU)
#define SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U)
#define SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U)
#define SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U)
#define SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU)
#define SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U)
#define SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U)
#define SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U)
#define SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU)
#define SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U)
#define SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U)
#define SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U)
#define SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU)
#define SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U)
#define SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U)
#define SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U)
#define SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU)
#define SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U)
#define SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U)
#define SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U)
#define SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU)
#define SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U)
#define SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U)
#define SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U)
#define SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU)
#define SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U)
#define SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U)
#define SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U)
#define SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU)
#define SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U)
#define SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U)
#define SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U)
#define SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU)
#define SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U)
#define SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U)
#define SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U)
#define SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU)
#define SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U)
#define SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U)
#define SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U)
#define SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU)
#define SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U)
#define SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U)
#define LIFEC_SAFE_BASE (0xE6120000U)
#define SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U)
#define SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU)
#define SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U)
#define SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U)
#define SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U)
#define SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU)
#define SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U)
#define SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U)
#define SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U)
#define SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU)
#define SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U)
#define SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U)
#define SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U)
#define SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU)
#define SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U)
#define SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U)
#define SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U)
#define SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU)
#define SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U)
#define SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U)
#define SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U)
#define SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU)
#define SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U)
#define SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U)
#define SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U)
#define SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU)
#define SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U)
#define SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U)
#define SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U)
#define SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU)
#define SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U)
#define SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U)
#define SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U)
#define SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU)
#define SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U)
#define SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U)
#define SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U)
#define SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU)
#define SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U)
#define SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U)
#define SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U)
#define SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU)
#define SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U)
#define SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U)
#define SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U)
#define SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU)
#define SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U)
#define SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U)
#define SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U)
#define SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU)
#define SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U)
#define SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U)
#define SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U)
#define SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU)
#define SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U)
#define SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U)
#endif /* LIFEC_REGISTERS_H */
plat/renesas/rcar/bl2_cpg_init.c
View file @ fc037ffc
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -7,8 +7,8 @@
#include <common/debug.h>
#include <lib/mmio.h>
#include "rcar_def.h"
#include "cpg_registers.h"
#include "rcar_def.h"
#include "rcar_private.h"
static void bl2_secure_cpg_init(void);
......@@ -77,7 +77,7 @@ static void bl2_secure_cpg_init(void)
stop_cr5 = 0xBFFFFFFFU;
#endif
/** Secure Module Stop Control Registers */
/* Secure Module Stop Control Registers */
cpg_write(SCMSTPCR0, 0xFFFFFFFFU);
cpg_write(SCMSTPCR1, 0xFFFFFFFFU);
cpg_write(SCMSTPCR2, stop_cr2);
......@@ -91,7 +91,7 @@ static void bl2_secure_cpg_init(void)
cpg_write(SCMSTPCR10, 0xFFFFFFFFU);
cpg_write(SCMSTPCR11, 0xFFFFFFFFU);
/** Secure Software Reset Access Enable Control Registers */
/* Secure Software Reset Access Enable Control Registers */
cpg_write(SCSRSTECR0, 0x00000000U);
cpg_write(SCSRSTECR1, 0x00000000U);
cpg_write(SCSRSTECR2, reset_cr2);
......@@ -152,7 +152,7 @@ static void bl2_system_cpg_init_h3(void)
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
static void bl2_realtime_cpg_init_m3(void)
{
/** Realtime Module Stop Control Registers */
/* Realtime Module Stop Control Registers */
cpg_write(RMSTPCR0, 0x00200000U);
cpg_write(RMSTPCR1, 0xFFFFFFFFU);
cpg_write(RMSTPCR2, 0x040E0FDCU);
......@@ -169,7 +169,7 @@ static void bl2_realtime_cpg_init_m3(void)
static void bl2_system_cpg_init_m3(void)
{
/** System Module Stop Control Registers */
/* System Module Stop Control Registers */
cpg_write(SMSTPCR0, 0x00200000U);
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x040E2FDCU);
......@@ -188,7 +188,7 @@ static void bl2_system_cpg_init_m3(void)
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
static void bl2_realtime_cpg_init_m3n(void)
{
/** Realtime Module Stop Control Registers */
/* Realtime Module Stop Control Registers */
cpg_write(RMSTPCR0, 0x00210000U);
cpg_write(RMSTPCR1, 0xFFFFFFFFU);
cpg_write(RMSTPCR2, 0x040E0FDCU);
......
plat/renesas/rcar/bl2_secure_setting.c
View file @ fc037ffc
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -18,230 +18,244 @@ static const struct {
uint32_t reg;
uint32_t val;
} lifec[] = {
/** LIFEC0 (SECURITY) settings */
/* Security attribute setting for master ports */
/* Bit 0: ARM realtime core (Cortex-R7) master port */
/* 0: Non-Secure */
{
SEC_SRC, 0x0000001EU},
/** Security attribute setting for slave ports 0 to 15 */
/* {SEC_SEL0, 0xFFFFFFFFU}, */
/* {SEC_SEL1, 0xFFFFFFFFU}, */
/* {SEC_SEL2, 0xFFFFFFFFU}, */
/* Bit19: AXI-Bus (Main Memory domain AXI) slave ports */
/* 0: registers accessed from secure resource only */
/* Bit 9: DBSC4 register access slave ports. */
/* 0: registers accessed from secure resource only. */
/*
* LIFEC0 (SECURITY) settings
* Security attribute setting for master ports
* Bit 0: ARM realtime core (Cortex-R7) master port
* 0: Non-Secure
*/
{ SEC_SRC, 0x0000001EU },
/*
* Security attribute setting for slave ports 0 to 15
* {SEC_SEL0, 0xFFFFFFFFU},
* {SEC_SEL1, 0xFFFFFFFFU},
* {SEC_SEL2, 0xFFFFFFFFU},
* Bit19: AXI-Bus (Main Memory domain AXI) slave ports
* 0: registers accessed from secure resource only
* Bit 9: DBSC4 register access slave ports.
* 0: registers accessed from secure resource only.
*/
#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
{
SEC_SEL3, 0xFFF7FDFFU},
#else
{
SEC_SEL3, 0xFFFFFFFFU},
#endif
/* {SEC_SEL4, 0xFFFFFFFFU}, */
/* Bit 6: Boot ROM slave ports. */
/* 0: registers accessed from secure resource only */
{
SEC_SEL5, 0xFFFFFFBFU},
/* Bit13: SCEG PKA (secure APB) slave ports */
/* 0: registers accessed from secure resource only */
/* 1: Reserved[R-Car E3] */
/* Bit12: SCEG PKA (public APB) slave ports */
/* 0: registers accessed from secure resource only */
/* 1: Reserved[R-Car E3] */
/* Bit10: SCEG Secure Core slave ports */
/* 0: registers accessed from secure resource only */
{ SEC_SEL3, 0xFFF7FDFFU },
#else /* LIFEC_DBSC_PROTECT_ENABLE == 1 */
{ SEC_SEL3, 0xFFFFFFFFU },
#endif /* LIFEC_DBSC_PROTECT_ENABLE == 1 */
/*
* {SEC_SEL4, 0xFFFFFFFFU},
* Bit 6: Boot ROM slave ports.
* 0: registers accessed from secure resource only
*/
{ SEC_SEL5, 0xFFFFFFBFU },
/*
* Bit13: SCEG PKA (secure APB) slave ports
* 0: registers accessed from secure resource only
* 1: Reserved[R-Car E3]
* Bit12: SCEG PKA (public APB) slave ports
* 0: registers accessed from secure resource only
* 1: Reserved[R-Car E3]
* Bit10: SCEG Secure Core slave ports
* 0: registers accessed from secure resource only
*/
#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
{
SEC_SEL6, 0xFFFFFBFFU},
#else
{
SEC_SEL6, 0xFFFFCBFFU},
#endif
/* {SEC_SEL7, 0xFFFFFFFFU}, */
/* {SEC_SEL8, 0xFFFFFFFFU}, */
/* {SEC_SEL9, 0xFFFFFFFFU}, */
/* {SEC_SEL10, 0xFFFFFFFFU}, */
/* {SEC_SEL11, 0xFFFFFFFFU}, */
/* {SEC_SEL12, 0xFFFFFFFFU}, */
/* Bit22: RPC slave ports. */
/* 0: registers accessed from secure resource only. */
{ SEC_SEL6, 0xFFFFFBFFU },
#else /* (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) */
{ SEC_SEL6, 0xFFFFCBFFU },
#endif /* (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3) */
/*
* {SEC_SEL7, 0xFFFFFFFFU},
* {SEC_SEL8, 0xFFFFFFFFU},
* {SEC_SEL9, 0xFFFFFFFFU},
* {SEC_SEL10, 0xFFFFFFFFU},
* {SEC_SEL11, 0xFFFFFFFFU},
* {SEC_SEL12, 0xFFFFFFFFU},
* Bit22: RPC slave ports.
* 0: registers accessed from secure resource only.
*/
#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
{SEC_SEL13, 0xFFBFFFFFU},
#endif
/* Bit27: System Timer (SCMT) slave ports */
/* 0: registers accessed from secure resource only */
/* Bit26: System Watchdog Timer (SWDT) slave ports */
/* 0: registers accessed from secure resource only */
{
SEC_SEL14, 0xF3FFFFFFU},
/* Bit13: RST slave ports. */
/* 0: registers accessed from secure resource only */
/* Bit 7: Life Cycle 0 slave ports */
/* 0: registers accessed from secure resource only */
{
SEC_SEL15, 0xFFFFFF3FU},
/** Security group 0 attribute setting for master ports 0 */
/** Security group 1 attribute setting for master ports 0 */
/* {SEC_GRP0CR0, 0x00000000U}, */
/* {SEC_GRP1CR0, 0x00000000U}, */
/** Security group 0 attribute setting for master ports 1 */
/** Security group 1 attribute setting for master ports 1 */
/* {SEC_GRP0CR1, 0x00000000U}, */
/* {SEC_GRP1CR1, 0x00000000U}, */
/** Security group 0 attribute setting for master ports 2 */
/** Security group 1 attribute setting for master ports 2 */
/* Bit17: SCEG Secure Core master ports. */
/* SecurityGroup3 */
{
SEC_GRP0CR2, 0x00020000U}, {
SEC_GRP1CR2, 0x00020000U},
/** Security group 0 attribute setting for master ports 3 */
/** Security group 1 attribute setting for master ports 3 */
/* {SEC_GRP0CR3, 0x00000000U}, */
/* {SEC_GRP1CR3, 0x00000000U}, */
/** Security group 0 attribute setting for slave ports 0 */
/** Security group 1 attribute setting for slave ports 0 */
/* {SEC_GRP0COND0, 0x00000000U}, */
/* {SEC_GRP1COND0, 0x00000000U}, */
/** Security group 0 attribute setting for slave ports 1 */
/** Security group 1 attribute setting for slave ports 1 */
/* {SEC_GRP0COND1, 0x00000000U}, */
/* {SEC_GRP1COND1, 0x00000000U}, */
/** Security group 0 attribute setting for slave ports 2 */
/** Security group 1 attribute setting for slave ports 2 */
/* {SEC_GRP0COND2, 0x00000000U}, */
/* {SEC_GRP1COND2, 0x00000000U}, */
/** Security group 0 attribute setting for slave ports 3 */
/** Security group 1 attribute setting for slave ports 3 */
/* Bit19: AXI-Bus (Main Memory domain AXI) slave ports. */
/* SecurityGroup3 */
/* Bit 9: DBSC4 register access slave ports. */
/* SecurityGroup3 */
{ SEC_SEL13, 0xFFBFFFFFU },
#endif /* (RCAR_RPC_HYPERFLASH_LOCKED == 1) */
/*
* Bit27: System Timer (SCMT) slave ports
* 0: registers accessed from secure resource only
* Bit26: System Watchdog Timer (SWDT) slave ports
* 0: registers accessed from secure resource only
*/
{ SEC_SEL14, 0xF3FFFFFFU },
/*
* Bit13: RST slave ports.
* 0: registers accessed from secure resource only
* Bit 7: Life Cycle 0 slave ports
* 0: registers accessed from secure resource only
*/
{ SEC_SEL15, 0xFFFFFF3FU },
/*
* Security group 0 attribute setting for master ports 0
* Security group 1 attribute setting for master ports 0
* {SEC_GRP0CR0, 0x00000000U},
* {SEC_GRP1CR0, 0x00000000U},
* Security group 0 attribute setting for master ports 1
* Security group 1 attribute setting for master ports 1
* {SEC_GRP0CR1, 0x00000000U},
* {SEC_GRP1CR1, 0x00000000U},
* Security group 0 attribute setting for master ports 2
* Security group 1 attribute setting for master ports 2
* Bit17: SCEG Secure Core master ports.
* SecurityGroup3
*/
{ SEC_GRP0CR2, 0x00020000U },
{ SEC_GRP1CR2, 0x00020000U },
/*
* Security group 0 attribute setting for master ports 3
* Security group 1 attribute setting for master ports 3
* {SEC_GRP0CR3, 0x00000000U},
* {SEC_GRP1CR3, 0x00000000U},
* Security group 0 attribute setting for slave ports 0
* Security group 1 attribute setting for slave ports 0
* {SEC_GRP0COND0, 0x00000000U},
* {SEC_GRP1COND0, 0x00000000U},
* Security group 0 attribute setting for slave ports 1
* Security group 1 attribute setting for slave ports 1
* {SEC_GRP0COND1, 0x00000000U},
* {SEC_GRP1COND1, 0x00000000U},
* Security group 0 attribute setting for slave ports 2
* Security group 1 attribute setting for slave ports 2
* {SEC_GRP0COND2, 0x00000000U},
* {SEC_GRP1COND2, 0x00000000U},
* Security group 0 attribute setting for slave ports 3
* Security group 1 attribute setting for slave ports 3
* Bit19: AXI-Bus (Main Memory domain AXI) slave ports.
* SecurityGroup3
* Bit 9: DBSC4 register access slave ports.
* SecurityGroup3
*/
#if (LIFEC_DBSC_PROTECT_ENABLE == 1)
{
SEC_GRP0COND3, 0x00080200U}, {
SEC_GRP1COND3, 0x00080200U},
#else
{
SEC_GRP0COND3, 0x00000000U}, {
SEC_GRP1COND3, 0x00000000U},
#endif
/** Security group 0 attribute setting for slave ports 4 */
/** Security group 1 attribute setting for slave ports 4 */
/* {SEC_GRP0COND4, 0x00000000U}, */
/* {SEC_GRP1COND4, 0x00000000U}, */
/** Security group 0 attribute setting for slave ports 5 */
/** Security group 1 attribute setting for slave ports 5 */
/* Bit 6: Boot ROM slave ports */
/* SecurityGroup3 */
{
SEC_GRP0COND5, 0x00000040U}, {
SEC_GRP1COND5, 0x00000040U},
/** Security group 0 attribute setting for slave ports 6 */
/** Security group 1 attribute setting for slave ports 6 */
/* Bit13: SCEG PKA (secure APB) slave ports */
/* SecurityGroup3 */
/* Reserved[R-Car E3] */
/* Bit12: SCEG PKA (public APB) slave ports */
/* SecurityGroup3 */
/* Reserved[R-Car E3] */
/* Bit10: SCEG Secure Core slave ports */
/* SecurityGroup3 */
{ SEC_GRP0COND3, 0x00080200U },
{ SEC_GRP1COND3, 0x00080200U },
#else /* (LIFEC_DBSC_PROTECT_ENABLE == 1) */
{ SEC_GRP0COND3, 0x00000000U },
{ SEC_GRP1COND3, 0x00000000U },
#endif /* (LIFEC_DBSC_PROTECT_ENABLE == 1) */
/*
* Security group 0 attribute setting for slave ports 4
* Security group 1 attribute setting for slave ports 4
* {SEC_GRP0COND4, 0x00000000U},
* {SEC_GRP1COND4, 0x00000000U},
* Security group 0 attribute setting for slave ports 5
* Security group 1 attribute setting for slave ports 5
* Bit 6: Boot ROM slave ports
* SecurityGroup3
*/
{ SEC_GRP0COND5, 0x00000040U },
{ SEC_GRP1COND5, 0x00000040U },
/*
* Security group 0 attribute setting for slave ports 6
* Security group 1 attribute setting for slave ports 6
* Bit13: SCEG PKA (secure APB) slave ports
* SecurityGroup3
* Reserved[R-Car E3]
* Bit12: SCEG PKA (public APB) slave ports
* SecurityGroup3
* Reserved[R-Car E3]
* Bit10: SCEG Secure Core slave ports
* SecurityGroup3
*/
#if RCAR_LSI == RCAR_E3
{
SEC_GRP0COND6, 0x00000400U}, {
SEC_GRP1COND6, 0x00000400U},
#else
{
SEC_GRP0COND6, 0x00003400U}, {
SEC_GRP1COND6, 0x00003400U},
#endif
/** Security group 0 attribute setting for slave ports 7 */
/** Security group 1 attribute setting for slave ports 7 */
/* {SEC_GRP0COND7, 0x00000000U}, */
/* {SEC_GRP1COND7, 0x00000000U}, */
/** Security group 0 attribute setting for slave ports 8 */
/** Security group 1 attribute setting for slave ports 8 */
/* {SEC_GRP0COND8, 0x00000000U}, */
/* {SEC_GRP1COND8, 0x00000000U}, */
/** Security group 0 attribute setting for slave ports 9 */
/** Security group 1 attribute setting for slave ports 9 */
/* {SEC_GRP0COND9, 0x00000000U}, */
/* {SEC_GRP1COND9, 0x00000000U}, */
/** Security group 0 attribute setting for slave ports 10 */
/** Security group 1 attribute setting for slave ports 10 */
/* {SEC_GRP0COND10, 0x00000000U}, */
/* {SEC_GRP1COND10, 0x00000000U}, */
/** Security group 0 attribute setting for slave ports 11 */
/** Security group 1 attribute setting for slave ports 11 */
/* {SEC_GRP0COND11, 0x00000000U}, */
/* {SEC_GRP1COND11, 0x00000000U}, */
/** Security group 0 attribute setting for slave ports 12 */
/** Security group 1 attribute setting for slave ports 12 */
/* {SEC_GRP0COND12, 0x00000000U}, */
/* {SEC_GRP1COND12, 0x00000000U}, */
/** Security group 0 attribute setting for slave ports 13 */
/** Security group 1 attribute setting for slave ports 13 */
/* Bit22: RPC slave ports. */
/* SecurityGroup3 */
{ SEC_GRP0COND6, 0x00000400U },
{ SEC_GRP1COND6, 0x00000400U },
#else /* RCAR_LSI == RCAR_E3 */
{ SEC_GRP0COND6, 0x00003400U },
{ SEC_GRP1COND6, 0x00003400U },
#endif /* RCAR_LSI == RCAR_E3 */
/*
* Security group 0 attribute setting for slave ports 7
* Security group 1 attribute setting for slave ports 7
* {SEC_GRP0COND7, 0x00000000U},
* {SEC_GRP1COND7, 0x00000000U},
* Security group 0 attribute setting for slave ports 8
* Security group 1 attribute setting for slave ports 8
* {SEC_GRP0COND8, 0x00000000U},
* {SEC_GRP1COND8, 0x00000000U},
* Security group 0 attribute setting for slave ports 9
* Security group 1 attribute setting for slave ports 9
* {SEC_GRP0COND9, 0x00000000U},
* {SEC_GRP1COND9, 0x00000000U},
* Security group 0 attribute setting for slave ports 10
* Security group 1 attribute setting for slave ports 10
* {SEC_GRP0COND10, 0x00000000U},
* {SEC_GRP1COND10, 0x00000000U},
* Security group 0 attribute setting for slave ports 11
* Security group 1 attribute setting for slave ports 11
* {SEC_GRP0COND11, 0x00000000U},
* {SEC_GRP1COND11, 0x00000000U},
* Security group 0 attribute setting for slave ports 12
* Security group 1 attribute setting for slave ports 12
* {SEC_GRP0COND12, 0x00000000U},
* {SEC_GRP1COND12, 0x00000000U},
* Security group 0 attribute setting for slave ports 13
* Security group 1 attribute setting for slave ports 13
* Bit22: RPC slave ports.
* SecurityGroup3
*/
#if (RCAR_RPC_HYPERFLASH_LOCKED == 1)
{SEC_GRP0COND13, 0x00400000U},
{SEC_GRP1COND13, 0x00400000U},
#endif
/** Security group 0 attribute setting for slave ports 14 */
/** Security group 1 attribute setting for slave ports 14 */
/* Bit26: System Timer (SCMT) slave ports */
/* SecurityGroup3 */
/* Bit27: System Watchdog Timer (SWDT) slave ports */
/* SecurityGroup3 */
{
SEC_GRP0COND14, 0x0C000000U}, {
SEC_GRP1COND14, 0x0C000000U},
/** Security group 0 attribute setting for slave ports 15 */
/** Security group 1 attribute setting for slave ports 15 */
/* Bit13: RST slave ports */
/* SecurityGroup3 */
/* Bit 7: Life Cycle 0 slave ports */
/* SecurityGroup3 */
/* Bit 6: TDBG slave ports */
/* SecurityGroup3 */
{
SEC_GRP0COND15, 0x000000C0U}, {
SEC_GRP1COND15, 0x000000C0U},
/** Security write protection attribute setting slave ports 0 */
/* {SEC_READONLY0, 0x00000000U}, */
/** Security write protection attribute setting slave ports 1 */
/* {SEC_READONLY1, 0x00000000U}, */
/** Security write protection attribute setting slave ports 2 */
/* {SEC_READONLY2, 0x00000000U}, */
/** Security write protection attribute setting slave ports 3 */
/* {SEC_READONLY3, 0x00000000U}, */
/** Security write protection attribute setting slave ports 4 */
/* {SEC_READONLY4, 0x00000000U}, */
/** Security write protection attribute setting slave ports 5 */
/* {SEC_READONLY5, 0x00000000U}, */
/** Security write protection attribute setting slave ports 6 */
/* {SEC_READONLY6, 0x00000000U}, */
/** Security write protection attribute setting slave ports 7 */
/* {SEC_READONLY7, 0x00000000U}, */
/** Security write protection attribute setting slave ports 8 */
/* {SEC_READONLY8, 0x00000000U}, */
/** Security write protection attribute setting slave ports 9 */
/* {SEC_READONLY9, 0x00000000U}, */
/** Security write protection attribute setting slave ports 10 */
/* {SEC_READONLY10, 0x00000000U}, */
/** Security write protection attribute setting slave ports 11 */
/* {SEC_READONLY11, 0x00000000U}, */
/** Security write protection attribute setting slave ports 12 */
/* {SEC_READONLY12, 0x00000000U}, */
/** Security write protection attribute setting slave ports 13 */
/* {SEC_READONLY13, 0x00000000U}, */
/** Security write protection attribute setting slave ports 14 */
/* {SEC_READONLY14, 0x00000000U}, */
/** Security write protection attribute setting slave ports 15 */
/* {SEC_READONLY15, 0x00000000U} */
{ SEC_GRP0COND13, 0x00400000U },
{ SEC_GRP1COND13, 0x00400000U },
#endif /* (RCAR_RPC_HYPERFLASH_LOCKED == 1) */
/*
* Security group 0 attribute setting for slave ports 14
* Security group 1 attribute setting for slave ports 14
* Bit26: System Timer (SCMT) slave ports
* SecurityGroup3
* Bit27: System Watchdog Timer (SWDT) slave ports
* SecurityGroup3
*/
{ SEC_GRP0COND14, 0x0C000000U },
{ SEC_GRP1COND14, 0x0C000000U },
/*
* Security group 0 attribute setting for slave ports 15
* Security group 1 attribute setting for slave ports 15
* Bit13: RST slave ports
* SecurityGroup3
* Bit 7: Life Cycle 0 slave ports
* SecurityGroup3
* Bit 6: TDBG slave ports
* SecurityGroup3
*/
{ SEC_GRP0COND15, 0x000000C0U },
{ SEC_GRP1COND15, 0x000000C0U },
/*
* Security write protection attribute setting slave ports 0
* {SEC_READONLY0, 0x00000000U},
* Security write protection attribute setting slave ports 1
* {SEC_READONLY1, 0x00000000U},
* Security write protection attribute setting slave ports 2
* {SEC_READONLY2, 0x00000000U},
* Security write protection attribute setting slave ports 3
* {SEC_READONLY3, 0x00000000U},
* Security write protection attribute setting slave ports 4
* {SEC_READONLY4, 0x00000000U},
* Security write protection attribute setting slave ports 5
* {SEC_READONLY5, 0x00000000U},
* Security write protection attribute setting slave ports 6
* {SEC_READONLY6, 0x00000000U},
* Security write protection attribute setting slave ports 7
* {SEC_READONLY7, 0x00000000U},
* Security write protection attribute setting slave ports 8
* {SEC_READONLY8, 0x00000000U},
* Security write protection attribute setting slave ports 9
* {SEC_READONLY9, 0x00000000U},
* Security write protection attribute setting slave ports 10
* {SEC_READONLY10, 0x00000000U},
* Security write protection attribute setting slave ports 11
* {SEC_READONLY11, 0x00000000U},
* Security write protection attribute setting slave ports 12
* {SEC_READONLY12, 0x00000000U},
* Security write protection attribute setting slave ports 13
* {SEC_READONLY13, 0x00000000U},
* Security write protection attribute setting slave ports 14
* {SEC_READONLY14, 0x00000000U},
* Security write protection attribute setting slave ports 15
* {SEC_READONLY15, 0x00000000U}
*/
};
/* AXI settings */
......@@ -249,78 +263,78 @@ static const struct {
uint32_t reg;
uint32_t val;
} axi[] = {
/* DRAM protection */
/* AXI dram protected area division */
{
AXI_DPTDIVCR0, 0x0E0403F0U}, {
AXI_DPTDIVCR1, 0x0E0407E0U}, {
AXI_DPTDIVCR2, 0x0E080000U}, {
AXI_DPTDIVCR3, 0x0E080000U}, {
AXI_DPTDIVCR4, 0x0E080000U}, {
AXI_DPTDIVCR5, 0x0E080000U}, {
AXI_DPTDIVCR6, 0x0E080000U}, {
AXI_DPTDIVCR7, 0x0E080000U}, {
AXI_DPTDIVCR8, 0x0E080000U}, {
AXI_DPTDIVCR9, 0x0E080000U}, {
AXI_DPTDIVCR10, 0x0E080000U}, {
AXI_DPTDIVCR11, 0x0E080000U}, {
AXI_DPTDIVCR12, 0x0E080000U}, {
AXI_DPTDIVCR13, 0x0E080000U}, {
AXI_DPTDIVCR14, 0x0E080000U},
/* AXI dram protected area setting */
{
AXI_DPTCR0, 0x0E000000U}, {
AXI_DPTCR1, 0x0E000E0EU}, {
AXI_DPTCR2, 0x0E000000U}, {
AXI_DPTCR3, 0x0E000000U}, {
AXI_DPTCR4, 0x0E000000U}, {
AXI_DPTCR5, 0x0E000000U}, {
AXI_DPTCR6, 0x0E000000U}, {
AXI_DPTCR7, 0x0E000000U}, {
AXI_DPTCR8, 0x0E000000U}, {
AXI_DPTCR9, 0x0E000000U}, {
AXI_DPTCR10, 0x0E000000U}, {
AXI_DPTCR11, 0x0E000000U}, {
AXI_DPTCR12, 0x0E000000U}, {
AXI_DPTCR13, 0x0E000000U}, {
AXI_DPTCR14, 0x0E000000U}, {
AXI_DPTCR15, 0x0E000000U},
/* SRAM ptotection */
/* AXI sram protected area division */
{
AXI_SPTDIVCR0, 0x0E0E6304U}, {
AXI_SPTDIVCR1, 0x0E0E6360U}, {
AXI_SPTDIVCR2, 0x0E0E6360U}, {
AXI_SPTDIVCR3, 0x0E0E6360U}, {
AXI_SPTDIVCR4, 0x0E0E6360U}, {
AXI_SPTDIVCR5, 0x0E0E6360U}, {
AXI_SPTDIVCR6, 0x0E0E6360U}, {
AXI_SPTDIVCR7, 0x0E0E6360U}, {
AXI_SPTDIVCR8, 0x0E0E6360U}, {
AXI_SPTDIVCR9, 0x0E0E6360U}, {
AXI_SPTDIVCR10, 0x0E0E6360U}, {
AXI_SPTDIVCR11, 0x0E0E6360U}, {
AXI_SPTDIVCR12, 0x0E0E6360U}, {
AXI_SPTDIVCR13, 0x0E0E6360U}, {
AXI_SPTDIVCR14, 0x0E0E6360U},
/* AXI sram protected area setting */
{
AXI_SPTCR0, 0x0E000E0EU}, {
AXI_SPTCR1, 0x0E000000U}, {
AXI_SPTCR2, 0x0E000000U}, {
AXI_SPTCR3, 0x0E000000U}, {
AXI_SPTCR4, 0x0E000000U}, {
AXI_SPTCR5, 0x0E000000U}, {
AXI_SPTCR6, 0x0E000000U}, {
AXI_SPTCR7, 0x0E000000U}, {
AXI_SPTCR8, 0x0E000000U}, {
AXI_SPTCR9, 0x0E000000U}, {
AXI_SPTCR10, 0x0E000000U}, {
AXI_SPTCR11, 0x0E000000U}, {
AXI_SPTCR12, 0x0E000000U}, {
AXI_SPTCR13, 0x0E000000U}, {
AXI_SPTCR14, 0x0E000000U}, {
AXI_SPTCR15, 0x0E000000U}
/*
* DRAM protection
* AXI dram protected area division
*/
{AXI_DPTDIVCR0, 0x0E0403F0U},
{AXI_DPTDIVCR1, 0x0E0407E0U},
{AXI_DPTDIVCR2, 0x0E080000U},
{AXI_DPTDIVCR3, 0x0E080000U},
{AXI_DPTDIVCR4, 0x0E080000U},
{AXI_DPTDIVCR5, 0x0E080000U},
{AXI_DPTDIVCR6, 0x0E080000U},
{AXI_DPTDIVCR7, 0x0E080000U},
{AXI_DPTDIVCR8, 0x0E080000U},
{AXI_DPTDIVCR9, 0x0E080000U},
{AXI_DPTDIVCR10, 0x0E080000U},
{AXI_DPTDIVCR11, 0x0E080000U},
{AXI_DPTDIVCR12, 0x0E080000U},
{AXI_DPTDIVCR13, 0x0E080000U},
{AXI_DPTDIVCR14, 0x0E080000U},
/* AXI dram protected area setting */
{AXI_DPTCR0, 0x0E000000U},
{AXI_DPTCR1, 0x0E000E0EU},
{AXI_DPTCR2, 0x0E000000U},
{AXI_DPTCR3, 0x0E000000U},
{AXI_DPTCR4, 0x0E000000U},
{AXI_DPTCR5, 0x0E000000U},
{AXI_DPTCR6, 0x0E000000U},
{AXI_DPTCR7, 0x0E000000U},
{AXI_DPTCR8, 0x0E000000U},
{AXI_DPTCR9, 0x0E000000U},
{AXI_DPTCR10, 0x0E000000U},
{AXI_DPTCR11, 0x0E000000U},
{AXI_DPTCR12, 0x0E000000U},
{AXI_DPTCR13, 0x0E000000U},
{AXI_DPTCR14, 0x0E000000U},
{AXI_DPTCR15, 0x0E000000U},
/*
* SRAM ptotection
* AXI sram protected area division
*/
{AXI_SPTDIVCR0, 0x0E0E6304U},
{AXI_SPTDIVCR1, 0x0E0E6360U},
{AXI_SPTDIVCR2, 0x0E0E6360U},
{AXI_SPTDIVCR3, 0x0E0E6360U},
{AXI_SPTDIVCR4, 0x0E0E6360U},
{AXI_SPTDIVCR5, 0x0E0E6360U},
{AXI_SPTDIVCR6, 0x0E0E6360U},
{AXI_SPTDIVCR7, 0x0E0E6360U},
{AXI_SPTDIVCR8, 0x0E0E6360U},
{AXI_SPTDIVCR9, 0x0E0E6360U},
{AXI_SPTDIVCR10, 0x0E0E6360U},
{AXI_SPTDIVCR11, 0x0E0E6360U},
{AXI_SPTDIVCR12, 0x0E0E6360U},
{AXI_SPTDIVCR13, 0x0E0E6360U},
{AXI_SPTDIVCR14, 0x0E0E6360U},
/* AXI sram protected area setting */
{AXI_SPTCR0, 0x0E000E0EU},
{AXI_SPTCR1, 0x0E000000U},
{AXI_SPTCR2, 0x0E000000U},
{AXI_SPTCR3, 0x0E000000U},
{AXI_SPTCR4, 0x0E000000U},
{AXI_SPTCR5, 0x0E000000U},
{AXI_SPTCR6, 0x0E000000U},
{AXI_SPTCR7, 0x0E000000U},
{AXI_SPTCR8, 0x0E000000U},
{AXI_SPTCR9, 0x0E000000U},
{AXI_SPTCR10, 0x0E000000U},
{AXI_SPTCR11, 0x0E000000U},
{AXI_SPTCR12, 0x0E000000U},
{AXI_SPTCR13, 0x0E000000U},
{AXI_SPTCR14, 0x0E000000U},
{AXI_SPTCR15, 0x0E000000U}
};
static void lifec_security_setting(void)
......@@ -342,11 +356,7 @@ static void axi_security_setting(void)
void bl2_secure_setting(void)
{
const uint32_t delay = 10;
lifec_security_setting();
axi_security_setting();
rcar_micro_delay(delay);
return;
rcar_micro_delay(10U);
}
plat/renesas/rcar/bl31_plat_setup.c
View file @ fc037ffc
......@@ -28,7 +28,7 @@ static const uint64_t BL31_RO_LIMIT = BL_CODE_END;
#if USE_COHERENT_MEM
static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
#endif
#endif /* USE_COHERENT_MEM */
extern void plat_rcar_gic_driver_init(void);
extern void plat_rcar_gic_init(void);
......@@ -84,11 +84,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
NOTICE("BL3-1 : Rev.%s\n", version_of_renesas);
#if RCAR_LSI != RCAR_D3
if (RCAR_CLUSTER_A53A57 == rcar_pwrc_get_cluster()) {
if (rcar_pwrc_get_cluster() == RCAR_CLUSTER_A53A57) {
plat_cci_init();
plat_cci_enable();
}
#endif
#endif /* RCAR_LSI != RCAR_D3 */
}
void bl31_plat_arch_setup(void)
......@@ -98,7 +98,7 @@ void bl31_plat_arch_setup(void)
BL31_RO_BASE, BL31_RO_LIMIT
#if USE_COHERENT_MEM
, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT
#endif
#endif /* USE_COHERENT_MEM */
);
rcar_pwrc_code_copy_to_system_ram();
}
......@@ -113,17 +113,20 @@ void bl31_platform_setup(void)
rcar_pwrc_setup();
#if 0
/* TODO: there is a broad number of rcar-gen3 SoC configurations; to
support all of them, Renesas use the pwrc driver to discover what
cores are on/off before announcing the topology.
This code hasnt been ported yet
*/
/*
* TODO: there is a broad number of rcar-gen3 SoC configurations; to
* support all of them, Renesas use the pwrc driver to discover what
* cores are on/off before announcing the topology.
* This code hasnt been ported yet
*/
rcar_setup_topology();
#endif
/* mask should match the kernel's MPIDR_HWID_BITMASK so the core can be
identified during cpuhotplug (check the kernel's psci migrate set of
functions */
/*
* mask should match the kernel's MPIDR_HWID_BITMASK so the core can be
* identified during cpuhotplug (check the kernel's psci migrate set of
* functions
*/
rcar_boot_mpidr = read_mpidr_el1() & 0x0000ffffU;
}
plat/renesas/rcar/include/registers/lifec_registers.h deleted 100644 → 0
View file @ 88e33b0c
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef LIFEC_REGISTERS_H
#define LIFEC_REGISTERS_H
#define LIFEC_SEC_BASE (0xE6110000U)
#define SEC_SRC (LIFEC_SEC_BASE + 0x0008U)
#define SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U)
#define SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U)
#define SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U)
#define SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU)
#define SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U)
#define SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU)
#define SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U)
#define SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U)
#define SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U)
#define SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU)
#define SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U)
#define SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U)
#define SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U)
#define SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU)
#define SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U)
#define SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U)
#define SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U)
#define SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU)
#define SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U)
#define SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U)
#define SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U)
#define SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU)
#define SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U)
#define SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U)
#define SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U)
#define SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU)
#define SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U)
#define SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U)
#define SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U)
#define SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU)
#define SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U)
#define SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U)
#define SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U)
#define SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU)
#define SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U)
#define SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U)
#define SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U)
#define SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU)
#define SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U)
#define SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U)
#define SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U)
#define SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU)
#define SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U)
#define SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U)
#define SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U)
#define SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU)
#define SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U)
#define SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U)
#define SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U)
#define SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU)
#define SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U)
#define SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U)
#define SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U)
#define SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU)
#define SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U)
#define SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U)
#define SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U)
#define SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU)
#define SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U)
#define SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U)
#define SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U)
#define SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU)
#define SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U)
#define SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U)
#define SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U)
#define SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU)
#define SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U)
#define SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U)
#define SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U)
#define SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU)
#define SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U)
#define SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U)
#define LIFEC_SAFE_BASE (0xE6120000U)
#define SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U)
#define SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU)
#define SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U)
#define SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U)
#define SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U)
#define SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU)
#define SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U)
#define SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U)
#define SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U)
#define SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU)
#define SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U)
#define SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U)
#define SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U)
#define SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU)
#define SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U)
#define SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U)
#define SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U)
#define SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU)
#define SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U)
#define SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U)
#define SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U)
#define SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU)
#define SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U)
#define SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U)
#define SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U)
#define SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU)
#define SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U)
#define SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U)
#define SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U)
#define SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU)
#define SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U)
#define SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U)
#define SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U)
#define SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU)
#define SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U)
#define SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U)
#define SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U)
#define SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU)
#define SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U)
#define SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U)
#define SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U)
#define SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU)
#define SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U)
#define SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U)
#define SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U)
#define SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU)
#define SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U)
#define SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U)
#define SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U)
#define SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU)
#define SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U)
#define SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U)
#define SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U)
#define SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU)
#define SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U)
#define SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U)
#endif /* LIFEC_REGISTERS_H */
plat/renesas/rcar/plat_pm.c
View file @ fc037ffc
......@@ -6,8 +6,6 @@
#include <errno.h>
#include <platform_def.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
......@@ -19,17 +17,18 @@
#include <plat/common/platform.h>
#include "iic_dvfs.h"
#include "platform_def.h"
#include "pwrc.h"
#include "rcar_def.h"
#include "rcar_private.h"
#include "ulcb_cpld.h"
#define DVFS_SET_VID_0V (0x00)
#define P_ALL_OFF (0x80)
#define KEEPON_DDR1C (0x08)
#define KEEPON_DDR0C (0x04)
#define KEEPON_DDR1 (0x02)
#define KEEPON_DDR0 (0x01)
#define DVFS_SET_VID_0V (0x00)
#define P_ALL_OFF (0x80)
#define KEEPON_DDR1C (0x08)
#define KEEPON_DDR0C (0x04)
#define KEEPON_DDR1 (0x02)
#define KEEPON_DDR0 (0x01)
#define SYSTEM_PWR_STATE(s) ((s)->pwr_domain_state[PLAT_MAX_PWR_LVL])
#define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1])
......@@ -200,20 +199,20 @@ static void __dead2 rcar_system_reset(void)
error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, KEEP10_MAGIC);
if (error) {
ERROR("Failed send KEEP10 magic ret=%d \n", error);
ERROR("Failed send KEEP10 magic ret=%d\n", error);
goto done;
}
error = rcar_iic_dvfs_receive(PMIC, BKUP_MODE_CNT, &mode);
if (error) {
ERROR("Failed recieve BKUP_Mode_Cnt ret=%d \n", error);
ERROR("Failed receive BKUP_Mode_Cnt ret=%d\n", error);
goto done;
}
mode |= KEEPON_DDR1C | KEEPON_DDR0C | KEEPON_DDR1 | KEEPON_DDR0;
error = rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, mode);
if (error) {
ERROR("Failed send KEEPON_DDRx ret=%d \n", error);
ERROR("Failed send KEEPON_DDRx ret=%d\n", error);
goto done;
}
......@@ -292,7 +291,7 @@ static const plat_psci_ops_t rcar_plat_psci_ops = {
.system_reset = rcar_system_reset,
.validate_power_state = rcar_validate_power_state,
#if RCAR_SYSTEM_SUSPEND
.get_sys_suspend_power_state = rcar_get_sys_suspend_power_state,
.get_sys_suspend_power_state = rcar_get_sys_suspend_power_state,
#endif
};
......
plat/renesas/rcar/plat_storage.c
View file @ fc037ffc
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <string.h>
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_storage.h>
#include <drivers/io/io_semihosting.h>
#include "io_common.h"
#include "io_rcar.h"
#include "io_memdrv.h"
#include "io_emmcdrv.h"
#include "io_private.h"
#include "io_rcar.h"
#include <platform_def.h>
static uintptr_t emmcdrv_dev_handle;
static uintptr_t memdrv_dev_handle;
......@@ -167,7 +166,7 @@ static int32_t open_rcar(const uintptr_t spec);
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
int32_t(*check) (const uintptr_t spec);
int32_t (*check)(const uintptr_t spec);
};
static const struct plat_io_policy policies[] = {
......@@ -305,7 +304,7 @@ static const struct plat_io_policy policies[] = {
(uintptr_t) &bl338_cert_file_spec,
&open_rcar}, {
#else
{
{
#endif
0, 0, 0}
};
......@@ -322,16 +321,11 @@ static io_drv_spec_t io_drv_spec_emmcdrv = {
0,
};
static struct plat_io_policy drv_policies[]
__attribute__ ((section(".data"))) = {
static struct plat_io_policy drv_policies[] __attribute__ ((section(".data"))) = {
/* FLASH_DEV_ID */
{
&memdrv_dev_handle,
(uintptr_t) &io_drv_spec_memdrv, &open_memmap,},
/* EMMC_DEV_ID */
{
&emmcdrv_dev_handle,
(uintptr_t) &io_drv_spec_emmcdrv, &open_emmcdrv,}
{ &memdrv_dev_handle, (uintptr_t) &io_drv_spec_memdrv, &open_memmap, },
/* EMMC_DEV_ID */
{ &emmcdrv_dev_handle, (uintptr_t) &io_drv_spec_emmcdrv, &open_emmcdrv, }
};
static int32_t open_rcar(const uintptr_t spec)
......
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