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Commit fc037ffc authored by Madhukar Pappireddy's avatar Madhukar Pappireddy Committed by TrustedFirmware Code Review
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Merge changes Id2b1822c,Ia9a563a1,I11f65d49,If9318a51,I46801b56, ... into integration 

* changes:
  drivers: renesas: Move plat common sources
  plat: renesas: Move headers and assembly files to common folder
  plat: renesas: rcar: include: Code cleanup
  plat: renesas:rcar: Fix checkpatch warnings
  plat: renesas: rcar: Fix checkpatch warnings
  plat: renesas:rcar: Code cleanup
  plat: renesas: rcar: Fix coding style
parents 88e33b0c be92e5a2
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plat/renesas/common/common.mk 0 → 100644
View file @ fc037ffc
#
# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
PROGRAMMABLE_RESET_ADDRESS := 0
COLD_BOOT_SINGLE_CPU := 1
ARM_CCI_PRODUCT_ID := 500
TRUSTED_BOARD_BOOT := 1
RESET_TO_BL31 := 1
GENERATE_COT := 1
BL2_AT_EL3 := 1
ENABLE_SVE_FOR_NS := 0
MULTI_CONSOLE_API := 1
CRASH_REPORTING := 1
HANDLE_EA_EL3_FIRST := 1
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
ifeq (${SPD},none)
SPD_NONE:=1
$(eval $(call add_define,SPD_NONE))
endif
# LSI setting common define
RCAR_H3:=0
RCAR_M3:=1
RCAR_M3N:=2
RCAR_E3:=3
RCAR_H3N:=4
RCAR_D3:=5
RCAR_V3M:=6
RCAR_AUTO:=99
$(eval $(call add_define,RCAR_H3))
$(eval $(call add_define,RCAR_M3))
$(eval $(call add_define,RCAR_M3N))
$(eval $(call add_define,RCAR_E3))
$(eval $(call add_define,RCAR_H3N))
$(eval $(call add_define,RCAR_D3))
$(eval $(call add_define,RCAR_V3M))
$(eval $(call add_define,RCAR_AUTO))
RCAR_CUT_10:=0
RCAR_CUT_11:=1
RCAR_CUT_13:=3
RCAR_CUT_20:=10
RCAR_CUT_30:=20
$(eval $(call add_define,RCAR_CUT_10))
$(eval $(call add_define,RCAR_CUT_11))
$(eval $(call add_define,RCAR_CUT_13))
$(eval $(call add_define,RCAR_CUT_20))
$(eval $(call add_define,RCAR_CUT_30))
# Enable workarounds for selected Cortex-A53 erratas.
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
# Enable workarounds for selected Cortex-A57 erratas.
ERRATA_A57_859972 := 1
ERRATA_A57_813419 := 1
PLAT_INCLUDES := -Iplat/renesas/common/include/registers \
-Iplat/renesas/common/include \
-Iplat/renesas/common
PLAT_BL_COMMON_SOURCES := drivers/renesas/common/iic_dvfs/iic_dvfs.c \
plat/renesas/common/rcar_common.c
RCAR_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c
BL2_SOURCES += ${RCAR_GIC_SOURCES} \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
${LIBFDT_SRCS} \
common/desc_image_load.c \
drivers/renesas/common/common.c \
drivers/io/io_storage.c
BL31_SOURCES += ${RCAR_GIC_SOURCES} \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
plat/common/plat_psci_common.c \
drivers/renesas/common/common.c \
drivers/arm/cci/cci.c
include lib/xlat_tables_v2/xlat_tables.mk
include drivers/auth/mbedtls/mbedtls_crypto.mk
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
plat/renesas/rcar/include/platform_def.h → plat/renesas/common/include/platform_def.h
View file @ fc037ffc
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -97,11 +97,13 @@
#define MAX_IO_DEVICES U(3)
#define MAX_IO_HANDLES U(4)
/*******************************************************************************
/*
******************************************************************************
* BL2 specific defines.
******************************************************************************/
/* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth. */
******************************************************************************
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth.
*/
#define RCAR_SYSRAM_BASE U(0xE6300000)
#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
#define BL2_LIMIT U(0xE6320000)
......@@ -121,11 +123,13 @@
#endif
#define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
/*******************************************************************************
/*
******************************************************************************
* BL31 specific defines.
******************************************************************************/
/* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL3-1 debug size plus a little space for growth. */
******************************************************************************
* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL3-1 debug size plus a little space for growth.
*/
#define BL31_BASE (RCAR_TRUSTED_SRAM_BASE)
#define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE + \
RCAR_TRUSTED_SRAM_SIZE)
......@@ -176,7 +180,7 @@
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
* caches. Such alignment ensures that two mailboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
......
plat/renesas/rcar/include/rcar_def.h → plat/renesas/common/include/rcar_def.h
View file @ fc037ffc
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -47,15 +47,19 @@
#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
#define BOOT_KIND_BASE (RCAR_SHARED_MEM_BASE + \
RCAR_SHARED_MEM_SIZE - 0x100)
/* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU */
/*
* The number of regions like RO(code), coherent and data required by
* different BL stages which need to be mapped in the MMU
*/
#if USE_COHERENT_MEM
#define RCAR_BL_REGIONS (3)
#else
#define RCAR_BL_REGIONS (2)
#endif
/* The RCAR_MAX_MMAP_REGIONS depend on the number of entries in rcar_mmap[]
* defined for each BL stage in rcar_common.c. */
/*
* The RCAR_MAX_MMAP_REGIONS depends on the number of entries in rcar_mmap[]
* defined for each BL stage in rcar_common.c.
*/
#if IMAGE_BL2
#define RCAR_MMAP_ENTRIES (9)
#endif
......@@ -75,7 +79,7 @@
/* BL31 */
#define RCAR_DEVICE_BASE DEVICE_RCAR_BASE
#define RCAR_DEVICE_SIZE (0x1A000000)
#define RCAR_LOG_RES_SIZE (512/8)
#define RCAR_LOG_RES_SIZE (64)
#define RCAR_LOG_HEADER_SIZE (16)
#define RCAR_LOG_OTHER_SIZE (RCAR_LOG_HEADER_SIZE + \
RCAR_LOG_RES_SIZE)
......@@ -139,8 +143,8 @@
#define RCAR_SYSCSR U(0xE6180000) /* SYSC status */
#define RCAR_PWRONCR3 U(0xE618014C) /* Power resume A53-SCU */
#define RCAR_PWRONCR5 U(0xE61801CC) /* Power resume A57-SCU */
#define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutof A53-SCU */
#define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutof A57-SCU */
#define RCAR_PWROFFCR3 U(0xE6180144) /* Power shutoff A53-SCU */
#define RCAR_PWROFFCR5 U(0xE61801C4) /* Power shutoff A57-SCU */
#define RCAR_PWRER3 U(0xE6180154) /* shutoff/resume error */
#define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */
#define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */
......
plat/renesas/rcar/include/rcar_private.h → plat/renesas/common/include/rcar_private.h
View file @ fc037ffc
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -7,12 +7,12 @@
#ifndef RCAR_PRIVATE_H
#define RCAR_PRIVATE_H
#include <platform_def.h>
#include <common/bl_common.h>
#include <lib/bakery_lock.h>
#include <lib/el3_runtime/cpu_data.h>
#include <platform_def.h>
typedef volatile struct mailbox {
unsigned long value __aligned(CACHE_WRITEBACK_GRANULE);
} mailbox_t;
......@@ -69,10 +69,11 @@ typedef struct rcar_cpu_data {
#define rcar_lock_release(_lock_arg) \
bakery_lock_release(_lock_arg, \
CPU_DATA_PLAT_PCPU_OFFSET + RCAR_CPU_DATA_LOCK_OFFSET)
/* Ensure that the size of the RCAR specific per-cpu data structure and the size
/*
* Ensure that the size of the RCAR specific per-cpu data structure and the size
* of the memory allocated in generic per-cpu data for the platform are the same
*/
CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(rcar_cpu_data_t),
CASSERT(sizeof(rcar_cpu_data_t) == PLAT_PCPU_DATA_SIZE,
rcar_pcpu_data_size_mismatch);
#endif
/*
......
plat/renesas/common/include/registers/lifec_registers.h 0 → 100644
View file @ fc037ffc
/*
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef LIFEC_REGISTERS_H
#define LIFEC_REGISTERS_H
#define LIFEC_SEC_BASE (0xE6110000U)
#define SEC_SRC (LIFEC_SEC_BASE + 0x0008U)
#define SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U)
#define SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U)
#define SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U)
#define SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU)
#define SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U)
#define SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU)
#define SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U)
#define SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U)
#define SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U)
#define SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU)
#define SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U)
#define SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U)
#define SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U)
#define SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU)
#define SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U)
#define SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U)
#define SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U)
#define SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU)
#define SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U)
#define SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U)
#define SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U)
#define SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU)
#define SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U)
#define SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U)
#define SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U)
#define SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU)
#define SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U)
#define SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U)
#define SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U)
#define SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU)
#define SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U)
#define SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U)
#define SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U)
#define SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU)
#define SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U)
#define SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U)
#define SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U)
#define SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU)
#define SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U)
#define SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U)
#define SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U)
#define SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU)
#define SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U)
#define SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U)
#define SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U)
#define SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU)
#define SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U)
#define SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U)
#define SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U)
#define SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU)
#define SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U)
#define SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U)
#define SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U)
#define SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU)
#define SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U)
#define SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U)
#define SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U)
#define SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU)
#define SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U)
#define SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U)
#define SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U)
#define SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU)
#define SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U)
#define SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U)
#define SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U)
#define SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU)
#define SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U)
#define SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U)
#define SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U)
#define SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU)
#define SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U)
#define SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U)
#define LIFEC_SAFE_BASE (0xE6120000U)
#define SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U)
#define SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU)
#define SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U)
#define SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U)
#define SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U)
#define SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU)
#define SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U)
#define SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U)
#define SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U)
#define SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU)
#define SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U)
#define SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U)
#define SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U)
#define SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU)
#define SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U)
#define SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U)
#define SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U)
#define SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU)
#define SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U)
#define SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U)
#define SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U)
#define SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU)
#define SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U)
#define SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U)
#define SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U)
#define SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU)
#define SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U)
#define SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U)
#define SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U)
#define SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU)
#define SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U)
#define SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U)
#define SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U)
#define SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU)
#define SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U)
#define SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U)
#define SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U)
#define SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU)
#define SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U)
#define SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U)
#define SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U)
#define SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU)
#define SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U)
#define SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U)
#define SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U)
#define SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU)
#define SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U)
#define SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U)
#define SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U)
#define SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU)
#define SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U)
#define SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U)
#define SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U)
#define SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU)
#define SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U)
#define SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U)
#endif /* LIFEC_REGISTERS_H */
plat/renesas/rcar/bl2_cpg_init.c
View file @ fc037ffc
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
......@@ -7,8 +7,8 @@
#include <common/debug.h>
#include <lib/mmio.h>
#include "rcar_def.h"
#include "cpg_registers.h"
#include "rcar_def.h"
#include "rcar_private.h"
static void bl2_secure_cpg_init(void);
......@@ -77,7 +77,7 @@ static void bl2_secure_cpg_init(void)
stop_cr5 = 0xBFFFFFFFU;
#endif
/** Secure Module Stop Control Registers */
/* Secure Module Stop Control Registers */
cpg_write(SCMSTPCR0, 0xFFFFFFFFU);
cpg_write(SCMSTPCR1, 0xFFFFFFFFU);
cpg_write(SCMSTPCR2, stop_cr2);
......@@ -91,7 +91,7 @@ static void bl2_secure_cpg_init(void)
cpg_write(SCMSTPCR10, 0xFFFFFFFFU);
cpg_write(SCMSTPCR11, 0xFFFFFFFFU);
/** Secure Software Reset Access Enable Control Registers */
/* Secure Software Reset Access Enable Control Registers */
cpg_write(SCSRSTECR0, 0x00000000U);
cpg_write(SCSRSTECR1, 0x00000000U);
cpg_write(SCSRSTECR2, reset_cr2);
......@@ -152,7 +152,7 @@ static void bl2_system_cpg_init_h3(void)
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3)
static void bl2_realtime_cpg_init_m3(void)
{
/** Realtime Module Stop Control Registers */
/* Realtime Module Stop Control Registers */
cpg_write(RMSTPCR0, 0x00200000U);
cpg_write(RMSTPCR1, 0xFFFFFFFFU);
cpg_write(RMSTPCR2, 0x040E0FDCU);
......@@ -169,7 +169,7 @@ static void bl2_realtime_cpg_init_m3(void)
static void bl2_system_cpg_init_m3(void)
{
/** System Module Stop Control Registers */
/* System Module Stop Control Registers */
cpg_write(SMSTPCR0, 0x00200000U);
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x040E2FDCU);
......@@ -188,7 +188,7 @@ static void bl2_system_cpg_init_m3(void)
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
static void bl2_realtime_cpg_init_m3n(void)
{
/** Realtime Module Stop Control Registers */
/* Realtime Module Stop Control Registers */
cpg_write(RMSTPCR0, 0x00210000U);
cpg_write(RMSTPCR1, 0xFFFFFFFFU);
cpg_write(RMSTPCR2, 0x040E0FDCU);
......
plat/renesas/rcar/bl2_secure_setting.c
View file @ fc037ffc
This diff is collapsed.
plat/renesas/rcar/bl31_plat_setup.c
View file @ fc037ffc
......@@ -28,7 +28,7 @@ static const uint64_t BL31_RO_LIMIT = BL_CODE_END;
#if USE_COHERENT_MEM
static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
#endif
#endif /* USE_COHERENT_MEM */
extern void plat_rcar_gic_driver_init(void);
extern void plat_rcar_gic_init(void);
......@@ -84,11 +84,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
NOTICE("BL3-1 : Rev.%s\n", version_of_renesas);
#if RCAR_LSI != RCAR_D3
if (RCAR_CLUSTER_A53A57 == rcar_pwrc_get_cluster()) {
if (rcar_pwrc_get_cluster() == RCAR_CLUSTER_A53A57) {
plat_cci_init();
plat_cci_enable();
}
#endif
#endif /* RCAR_LSI != RCAR_D3 */
}
void bl31_plat_arch_setup(void)
......@@ -98,7 +98,7 @@ void bl31_plat_arch_setup(void)
BL31_RO_BASE, BL31_RO_LIMIT
#if USE_COHERENT_MEM
, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT
#endif
#endif /* USE_COHERENT_MEM */
);
rcar_pwrc_code_copy_to_system_ram();
}
......@@ -113,17 +113,20 @@ void bl31_platform_setup(void)
rcar_pwrc_setup();
#if 0
/* TODO: there is a broad number of rcar-gen3 SoC configurations; to
support all of them, Renesas use the pwrc driver to discover what
cores are on/off before announcing the topology.
This code hasnt been ported yet
/*
* TODO: there is a broad number of rcar-gen3 SoC configurations; to
* support all of them, Renesas use the pwrc driver to discover what
* cores are on/off before announcing the topology.
* This code hasnt been ported yet
*/
rcar_setup_topology();
#endif
/* mask should match the kernel's MPIDR_HWID_BITMASK so the core can be
identified during cpuhotplug (check the kernel's psci migrate set of
functions */
/*
* mask should match the kernel's MPIDR_HWID_BITMASK so the core can be
* identified during cpuhotplug (check the kernel's psci migrate set of
* functions
*/
rcar_boot_mpidr = read_mpidr_el1() & 0x0000ffffU;
}
plat/renesas/rcar/include/registers/lifec_registers.h deleted 100644 → 0
View file @ 88e33b0c
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef LIFEC_REGISTERS_H
#define LIFEC_REGISTERS_H
#define LIFEC_SEC_BASE (0xE6110000U)
#define SEC_SRC (LIFEC_SEC_BASE + 0x0008U)
#define SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U)
#define SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U)
#define SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U)
#define SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU)
#define SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U)
#define SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU)
#define SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U)
#define SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U)
#define SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U)
#define SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU)
#define SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U)
#define SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U)
#define SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U)
#define SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU)
#define SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U)
#define SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U)
#define SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U)
#define SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU)
#define SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U)
#define SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U)
#define SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U)
#define SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU)
#define SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U)
#define SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U)
#define SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U)
#define SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU)
#define SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U)
#define SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U)
#define SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U)
#define SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU)
#define SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U)
#define SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U)
#define SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U)
#define SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU)
#define SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U)
#define SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U)
#define SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U)
#define SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU)
#define SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U)
#define SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U)
#define SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U)
#define SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU)
#define SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U)
#define SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U)
#define SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U)
#define SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU)
#define SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U)
#define SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U)
#define SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U)
#define SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU)
#define SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U)
#define SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U)
#define SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U)
#define SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU)
#define SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U)
#define SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U)
#define SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U)
#define SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU)
#define SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U)
#define SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U)
#define SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U)
#define SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU)
#define SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U)
#define SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U)
#define SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U)
#define SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU)
#define SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U)
#define SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U)
#define SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U)
#define SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU)
#define SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U)
#define SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U)
#define LIFEC_SAFE_BASE (0xE6120000U)
#define SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U)
#define SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU)
#define SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U)
#define SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U)
#define SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U)
#define SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU)
#define SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U)
#define SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U)
#define SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U)
#define SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU)
#define SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U)
#define SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U)
#define SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U)
#define SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU)
#define SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U)
#define SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U)
#define SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U)
#define SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU)
#define SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U)
#define SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U)
#define SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U)
#define SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU)
#define SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U)
#define SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U)
#define SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U)
#define SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU)
#define SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U)
#define SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U)
#define SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U)
#define SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU)
#define SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U)
#define SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U)
#define SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U)
#define SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU)
#define SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U)
#define SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U)
#define SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U)
#define SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU)
#define SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U)
#define SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U)
#define SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U)
#define SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU)
#define SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U)
#define SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U)
#define SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U)
#define SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU)
#define SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U)
#define SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U)
#define SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U)
#define SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU)
#define SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U)
#define SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U)
#define SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U)
#define SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU)
#define SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U)
#define SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U)
#endif /* LIFEC_REGISTERS_H */
plat/renesas/rcar/plat_pm.c
View file @ fc037ffc
......@@ -6,8 +6,6 @@
#include <errno.h>
#include <platform_def.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
......@@ -19,6 +17,7 @@
#include <plat/common/platform.h>
#include "iic_dvfs.h"
#include "platform_def.h"
#include "pwrc.h"
#include "rcar_def.h"
#include "rcar_private.h"
......@@ -200,20 +199,20 @@ static void __dead2 rcar_system_reset(void)
error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, KEEP10_MAGIC);
if (error) {
ERROR("Failed send KEEP10 magic ret=%d \n", error);
ERROR("Failed send KEEP10 magic ret=%d\n", error);
goto done;
}
error = rcar_iic_dvfs_receive(PMIC, BKUP_MODE_CNT, &mode);
if (error) {
ERROR("Failed recieve BKUP_Mode_Cnt ret=%d \n", error);
ERROR("Failed receive BKUP_Mode_Cnt ret=%d\n", error);
goto done;
}
mode |= KEEPON_DDR1C | KEEPON_DDR0C | KEEPON_DDR1 | KEEPON_DDR0;
error = rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, mode);
if (error) {
ERROR("Failed send KEEPON_DDRx ret=%d \n", error);
ERROR("Failed send KEEPON_DDRx ret=%d\n", error);
goto done;
}
......
plat/renesas/rcar/plat_storage.c
View file @ fc037ffc
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <string.h>
#include <platform_def.h>
#include <common/debug.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_storage.h>
#include <drivers/io/io_semihosting.h>
#include "io_common.h"
#include "io_rcar.h"
#include "io_memdrv.h"
#include "io_emmcdrv.h"
#include "io_private.h"
#include "io_rcar.h"
#include <platform_def.h>
static uintptr_t emmcdrv_dev_handle;
static uintptr_t memdrv_dev_handle;
......@@ -167,7 +166,7 @@ static int32_t open_rcar(const uintptr_t spec);
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
int32_t(*check) (const uintptr_t spec);
int32_t (*check)(const uintptr_t spec);
};
static const struct plat_io_policy policies[] = {
......@@ -322,16 +321,11 @@ static io_drv_spec_t io_drv_spec_emmcdrv = {
0,
};
static struct plat_io_policy drv_policies[]
__attribute__ ((section(".data"))) = {
static struct plat_io_policy drv_policies[] __attribute__ ((section(".data"))) = {
/* FLASH_DEV_ID */
{
&memdrv_dev_handle,
(uintptr_t) &io_drv_spec_memdrv, &open_memmap,},
{ &memdrv_dev_handle, (uintptr_t) &io_drv_spec_memdrv, &open_memmap, },
/* EMMC_DEV_ID */
{
&emmcdrv_dev_handle,
(uintptr_t) &io_drv_spec_emmcdrv, &open_emmcdrv,}
{ &emmcdrv_dev_handle, (uintptr_t) &io_drv_spec_emmcdrv, &open_emmcdrv, }
};
static int32_t open_rcar(const uintptr_t spec)
......
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