Commit fe23b15d authored by Sandrine Bailleux's avatar Sandrine Bailleux
Browse files

juno: Add support for BL3-2 image

This patch implements the TSP on Juno. It executes from Secure RAM.

Also, the other bootloader images (i.e. BL1 R/W, BL2 and BL3-1) have
been moved around. The reason is, although there was enough space
overall to store the TSP in SRAM, there was no contiguous free chunk
of SRAM big enough to hold it.

This patch keeps the overall memory layout (i.e. keeping BL1 R/W at
the bottom, BL2 at the top and BL3-1 in between) but moves the base
addresses of all the bootloader images in such a way that:
 - memory fragmentation is reduced enough to fit BL3-2 in;
 - new base addresses are suitable for release builds as well as debug
   ones;
 - each image has a few extra kilobytes for future growth.
   BL3-1 and BL3-2 are the images which received the biggest slice
   of the cake since they will most probably grow the most.

A few useful numbers for reference (valid at the time of this patch):
        |-----------------------|-------------------------------
        |  image size (debug)   |  extra space for the future
--------|-----------------------|-------------------------------
BL1 R/W |         28 KB         |            4 KB
BL2     |         48 KB         |            4 KB
BL3-1   |         96 KB         |            8 KB
BL3-2   |         56 KB         |            8 KB
--------|-----------------------|-------------------------------
Total   |        228 KB         |           24 KB       = 252 KB
--------|-----------------------|-------------------------------

Note: On Juno, although the Secure RAM is 256 KB, the first 4KB
are reserved for the AP/SCP mailboxes.

Change-Id: I999ec39589c45beabe1ecd772641623e58569a6e
parent 7795260a
#
# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
#
# Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# Neither the name of ARM nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific
# prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
# TSP source files specific to Juno platform
BL32_SOURCES += plat/common/aarch64/platform_mp_stack.S \
plat/juno/bl32_plat_setup.c \
plat/juno/aarch64/plat_common.c \
plat/juno/aarch64/plat_helpers.S
......@@ -177,8 +177,20 @@ void bl2_platform_setup()
bl2_to_bl31_args.bl33_meminfo.total_size = DRAM_SIZE;
bl2_to_bl31_args.bl33_meminfo.free_base = DRAM_BASE;
bl2_to_bl31_args.bl33_meminfo.free_size = DRAM_SIZE;
bl2_to_bl31_args.bl33_meminfo.attr = 0;
bl2_to_bl31_args.bl33_meminfo.attr = BOT_LOAD;
bl2_to_bl31_args.bl33_meminfo.next = 0;
/* Populate the extents of memory available for loading BL3-2 */
bl2_to_bl31_args.bl32_meminfo.total_base = BL32_BASE;
bl2_to_bl31_args.bl32_meminfo.free_base = BL32_BASE;
bl2_to_bl31_args.bl32_meminfo.total_size =
(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
bl2_to_bl31_args.bl32_meminfo.free_size =
(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
bl2_to_bl31_args.bl32_meminfo.attr = BOT_LOAD;
bl2_to_bl31_args.bl32_meminfo.next = 0;
}
/*******************************************************************************
......
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <bl_common.h>
#include <bl32.h>
#include <console.h>
#include <platform.h>
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
*/
#define BL32_RO_BASE (unsigned long)(&__RO_START__)
#define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
/* Data structure which holds the extents of the trusted SRAM for BL3-2 */
static meminfo_t bl32_tzdram_layout
__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
section("tzfw_coherent_mem")));
meminfo_t *bl32_plat_sec_mem_layout(void)
{
return &bl32_tzdram_layout;
}
/*******************************************************************************
* BL1 has passed the extents of the trusted SRAM that's at BL3-2's disposal.
* Initialize the BL3-2 data structure with the memory extends and initialize
* the UART
******************************************************************************/
void bl32_early_platform_setup(meminfo_t *mem_layout, void *data)
{
/*
* Initialize a different console than already in use to display
* messages from TSP
*/
console_init(PL011_UART1_BASE);
/* Setup the BL3-2 memory layout */
bl32_tzdram_layout.total_base = mem_layout->total_base;
bl32_tzdram_layout.total_size = mem_layout->total_size;
bl32_tzdram_layout.free_base = mem_layout->free_base;
bl32_tzdram_layout.free_size = mem_layout->free_size;
bl32_tzdram_layout.attr = mem_layout->attr;
bl32_tzdram_layout.next = 0;
}
/*******************************************************************************
* Perform platform specific setup placeholder
******************************************************************************/
void bl32_platform_setup(void)
{
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this only intializes the MMU
******************************************************************************/
void bl32_plat_arch_setup(void)
{
configure_mmu(&bl32_tzdram_layout,
BL32_RO_BASE,
BL32_RO_LIMIT,
BL32_COHERENT_RAM_BASE,
BL32_COHERENT_RAM_LIMIT);
}
/*
* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
ASSERT(__BL32_END__ <= BL2_BASE, "BL3-2 image overlaps BL2 image.")
......@@ -68,6 +68,11 @@ static const io_file_spec_t bl31_file_spec = {
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl32_file_spec = {
.path = BL32_IMAGE_NAME,
.mode = FOPEN_MODE_RB
};
static const io_file_spec_t bl33_file_spec = {
.path = BL33_IMAGE_NAME,
.mode = FOPEN_MODE_RB
......@@ -104,6 +109,11 @@ static const struct plat_io_policy policies[] = {
&fip_dev_handle,
(uintptr_t)&bl31_file_spec,
open_fip
}, {
BL32_IMAGE_NAME,
&fip_dev_handle,
(uintptr_t)&bl32_file_spec,
open_fip
}, {
BL33_IMAGE_NAME,
&fip_dev_handle,
......
......@@ -171,12 +171,12 @@
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
#define BL2_BASE 0x0402a000
#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xd000)
/*******************************************************************************
* BL3-1 specific defines.
******************************************************************************/
#define BL31_BASE 0x0400C000
#define BL31_BASE (TZRAM_BASE + 0x8000)
/*******************************************************************************
* BL3-0 specific defines.
......@@ -186,10 +186,11 @@
#define BL30_BASE BL31_BASE
/*******************************************************************************
* Workaround for issue #68
* We don't support BL3-2 on Juno yet
* BL3-2 specific defines.
******************************************************************************/
#define BL32_BASE 0
#define TSP_SEC_MEM_BASE TZRAM_BASE
#define TSP_SEC_MEM_SIZE TZRAM_SIZE
#define BL32_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1d000)
/*******************************************************************************
* Platform specific page table and MMU setup constants
......
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