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Commit fe877779 authored by Caesar Wang's avatar Caesar Wang
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rockchip: rk3399: add dram driver 

add dram driver, and kernel can through sip function talk to bl31 to
do ddr frequency scaling. and ddr auto powerdown.

Change-Id: I0d0f2869aed95e336c6e23ba96a9310985c84840
parent 50990186
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plat/rockchip/rk3399/drivers/dram/dcf_code.inc 0 → 100644
View file @ fe877779
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plat/rockchip/rk3399/drivers/dram/dram.c 0 → 100644
View file @ fe877779
This diff is collapsed.
plat/rockchip/rk3399/drivers/dram/dram.h 0 → 100644
View file @ fe877779
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SOC_ROCKCHIP_RK3399_SDRAM_H__
#define __SOC_ROCKCHIP_RK3399_SDRAM_H__
struct rk3399_ddr_cic_regs {
uint32_t cic_ctrl0;
uint32_t cic_ctrl1;
uint32_t cic_idle_th;
uint32_t cic_cg_wait_th;
uint32_t cic_status0;
uint32_t cic_status1;
uint32_t cic_ctrl2;
uint32_t cic_ctrl3;
uint32_t cic_ctrl4;
};
/* DENALI_CTL_00 */
#define START (1)
/* DENALI_CTL_68 */
#define PWRUP_SREFRESH_EXIT (1 << 16)
/* DENALI_CTL_274 */
#define MEM_RST_VALID (1)
struct rk3399_ddr_pctl_regs {
uint32_t denali_ctl[332];
};
struct rk3399_ddr_publ_regs {
uint32_t denali_phy[959];
};
#define PHY_DRV_ODT_Hi_Z (0x0)
#define PHY_DRV_ODT_240 (0x1)
#define PHY_DRV_ODT_120 (0x8)
#define PHY_DRV_ODT_80 (0x9)
#define PHY_DRV_ODT_60 (0xc)
#define PHY_DRV_ODT_48 (0xd)
#define PHY_DRV_ODT_40 (0xe)
#define PHY_DRV_ODT_34_3 (0xf)
struct rk3399_ddr_pi_regs {
uint32_t denali_pi[200];
};
union noc_ddrtiminga0 {
uint32_t d32;
struct {
unsigned acttoact : 6;
unsigned reserved0 : 2;
unsigned rdtomiss : 6;
unsigned reserved1 : 2;
unsigned wrtomiss : 6;
unsigned reserved2 : 2;
unsigned readlatency : 8;
} b;
};
union noc_ddrtimingb0 {
uint32_t d32;
struct {
unsigned rdtowr : 5;
unsigned reserved0 : 3;
unsigned wrtord : 5;
unsigned reserved1 : 3;
unsigned rrd : 4;
unsigned reserved2 : 4;
unsigned faw : 6;
unsigned reserved3 : 2;
} b;
};
union noc_ddrtimingc0 {
uint32_t d32;
struct {
unsigned burstpenalty : 4;
unsigned reserved0 : 4;
unsigned wrtomwr : 6;
unsigned reserved1 : 18;
} b;
};
union noc_devtodev0 {
uint32_t d32;
struct {
unsigned busrdtord : 3;
unsigned reserved0 : 1;
unsigned busrdtowr : 3;
unsigned reserved1 : 1;
unsigned buswrtord : 3;
unsigned reserved2 : 1;
unsigned buswrtowr : 3;
unsigned reserved3 : 17;
} b;
};
union noc_ddrmode {
uint32_t d32;
struct {
unsigned autoprecharge : 1;
unsigned bypassfiltering : 1;
unsigned fawbank : 1;
unsigned burstsize : 2;
unsigned mwrsize : 2;
unsigned reserved2 : 1;
unsigned forceorder : 8;
unsigned forceorderstate : 8;
unsigned reserved3 : 8;
} b;
};
struct rk3399_msch_regs {
uint32_t coreid;
uint32_t revisionid;
uint32_t ddrconf;
uint32_t ddrsize;
union noc_ddrtiminga0 ddrtiminga0;
union noc_ddrtimingb0 ddrtimingb0;
union noc_ddrtimingc0 ddrtimingc0;
union noc_devtodev0 devtodev0;
uint32_t reserved0[(0x110-0x20)/4];
union noc_ddrmode ddrmode;
uint32_t reserved1[(0x1000-0x114)/4];
uint32_t agingx0;
};
struct rk3399_msch_timings {
union noc_ddrtiminga0 ddrtiminga0;
union noc_ddrtimingb0 ddrtimingb0;
union noc_ddrtimingc0 ddrtimingc0;
union noc_devtodev0 devtodev0;
union noc_ddrmode ddrmode;
uint32_t agingx0;
};
#if 1
struct rk3399_sdram_channel {
unsigned char rank;
/* col = 0, means this channel is invalid */
unsigned char col;
/* 3:8bank, 2:4bank */
unsigned char bk;
/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned char bw;
/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
unsigned char dbw;
/* row_3_4 = 1: 6Gb or 12Gb die
* row_3_4 = 0: normal die, power of 2
*/
unsigned char row_3_4;
unsigned char cs0_row;
unsigned char cs1_row;
uint32_t ddrconfig;
struct rk3399_msch_timings noc_timings;
};
struct rk3399_sdram_params {
struct rk3399_sdram_channel ch[2];
uint32_t ddr_freq;
unsigned char dramtype;
unsigned char num_channels;
unsigned char stride;
unsigned char odt;
struct rk3399_ddr_pctl_regs pctl_regs;
struct rk3399_ddr_pi_regs pi_regs;
struct rk3399_ddr_publ_regs phy_regs;
};
#endif
struct rk3399_sdram_channel_config {
uint32_t bus_width;
uint32_t cs_cnt;
uint32_t cs0_row;
uint32_t cs1_row;
uint32_t bank;
uint32_t col;
uint32_t each_die_bus_width;
uint32_t each_die_6gb_or_12gb;
};
struct rk3399_sdram_config {
struct rk3399_sdram_channel_config ch[2];
uint32_t dramtype;
uint32_t channal_num;
};
struct rk3399_sdram_default_config {
unsigned char bl;
/* 1:auto precharge, 0:never auto precharge */
unsigned char ap;
/* dram driver strength */
unsigned char dramds;
/* dram ODT, if odt=0, this parameter invalid */
unsigned char dramodt;
/* ca ODT, if odt=0, this parameter invalid
* only used by LPDDR4
*/
unsigned char caodt;
unsigned char burst_ref_cnt;
/* zqcs period, unit(s) */
unsigned char zqcsi;
};
struct ddr_dts_config_timing {
uint32_t ddr3_speed_bin;
uint32_t pd_idle;
uint32_t sr_idle;
uint32_t sr_mc_gate_idle;
uint32_t srpd_lite_idle;
uint32_t standby_idle;
uint32_t ddr3_dll_dis_freq;
uint32_t phy_dll_dis_freq;
uint32_t ddr3_odt_dis_freq;
uint32_t ddr3_drv;
uint32_t ddr3_odt;
uint32_t phy_ddr3_ca_drv;
uint32_t phy_ddr3_dq_drv;
uint32_t phy_ddr3_odt;
uint32_t lpddr3_odt_dis_freq;
uint32_t lpddr3_drv;
uint32_t lpddr3_odt;
uint32_t phy_lpddr3_ca_drv;
uint32_t phy_lpddr3_dq_drv;
uint32_t phy_lpddr3_odt;
uint32_t lpddr4_odt_dis_freq;
uint32_t lpddr4_drv;
uint32_t lpddr4_dq_odt;
uint32_t lpddr4_ca_odt;
uint32_t phy_lpddr4_ca_drv;
uint32_t phy_lpddr4_ck_cs_drv;
uint32_t phy_lpddr4_dq_drv;
uint32_t phy_lpddr4_odt;
uint32_t available;
};
struct drv_odt_lp_config {
uint32_t ddr3_speed_bin;
uint32_t pd_idle;
uint32_t sr_idle;
uint32_t sr_mc_gate_idle;
uint32_t srpd_lite_idle;
uint32_t standby_idle;
uint32_t ddr3_dll_dis_freq;/* for ddr3 only */
uint32_t phy_dll_dis_freq;
uint32_t odt_dis_freq;
uint32_t dram_side_drv;
uint32_t dram_side_dq_odt;
uint32_t dram_side_ca_odt;
uint32_t phy_side_ca_drv;
uint32_t phy_side_ck_cs_drv;
uint32_t phy_side_dq_drv;
uint32_t phy_side_odt;
};
#define KHz (1000)
#define MHz (1000*KHz)
#define GHz (1000*MHz)
#define PI_CA_TRAINING (1 << 0)
#define PI_WRITE_LEVELING (1 << 1)
#define PI_READ_GATE_TRAINING (1 << 2)
#define PI_READ_LEVELING (1 << 3)
#define PI_WDQ_LEVELING (1 << 4)
#define PI_FULL_TARINING (0xff)
#define READ_CH_CNT(val) (1+((val>>12)&0x1))
#define READ_CH_INFO(val) ((val>>28)&0x3)
/* row_3_4:0=normal, 1=6Gb or 12Gb */
#define READ_CH_ROW_INFO(val, ch) ((val>>(30+(ch)))&0x1)
#define READ_DRAMTYPE_INFO(val) ((val>>13)&0x7)
#define READ_CS_INFO(val, ch) ((((val)>>(11+(ch)*16))&0x1)+1)
#define READ_BW_INFO(val, ch) (2>>(((val)>>(2+(ch)*16))&0x3))
#define READ_COL_INFO(val, ch) (9+(((val)>>(9+(ch)*16))&0x3))
#define READ_BK_INFO(val, ch) (3-(((val)>>(8+(ch)*16))&0x1))
#define READ_CS0_ROW_INFO(val, ch) (13+(((val)>>(6+(ch)*16))&0x3))
#define READ_CS1_ROW_INFO(val, ch) (13+(((val)>>(4+(ch)*16))&0x3))
#define READ_DIE_BW_INFO(val, ch) (2>>((val>>((ch)*16))&0x3))
#define __sramdata __attribute__((section(".sram.data")))
#define __sramconst __attribute__((section(".sram.rodata")))
#define __sramlocalfunc __attribute__((section(".sram.text")))
#define __sramfunc __attribute__((section(".sram.text"))) \
__attribute__((noinline))
#define DDR_SAVE_SP(save_sp) (save_sp = ddr_save_sp(((uint32_t)\
(SRAM_CODE_BASE + 0x2000) & (~7))))
#define DDR_RESTORE_SP(save_sp) ddr_save_sp(save_sp)
void ddr_init(void);
uint64_t ddr_set_rate(uint64_t hz);
uint64_t ddr_round_rate(uint64_t hz);
uint64_t ddr_get_rate(void);
void clr_dcf_irq(void);
uint64_t dts_timing_receive(uint64_t timing, uint64_t index);
#endif
plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c 0 → 100644
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plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h 0 → 100644
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This diff is collapsed.
plat/rockchip/rk3399/drivers/soc/soc.h
View file @ fe877779
......@@ -48,6 +48,12 @@
#define NO_PLL_BYPASS (0x00)
#define NO_PLL_PWRDN (0x00)
#define FBDIV(n) ((0xfff << 16) | n)
#define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12))
#define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8))
#define REFDIV(n) ((0x3F << 16) | n)
#define PLL_LOCK(n) ((n >> 31) & 0x1)
#define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\
PLL_MODE_MSK, PLL_MODE_SHIFT)
......@@ -107,6 +113,31 @@ struct deepsleep_data_s {
uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
};
/**************************************************
* pmugrf reg, offset
**************************************************/
#define PMUGRF_OSREG(n) (0x300 + (n) * 4)
/**************************************************
* DCF reg, offset
**************************************************/
#define DCF_DCF_CTRL 0x0
#define DCF_DCF_ADDR 0x8
#define DCF_DCF_ISR 0xc
#define DCF_DCF_TOSET 0x14
#define DCF_DCF_TOCMD 0x18
#define DCF_DCF_CMD_CFG 0x1c
/* DCF_DCF_ISR */
#define DCF_TIMEOUT (1 << 2)
#define DCF_ERR (1 << 1)
#define DCF_DONE (1 << 0)
/* DCF_DCF_CTRL */
#define DCF_VOP_HW_EN (1 << 2)
#define DCF_STOP (1 << 1)
#define DCF_START (1 << 0)
#define CYCL_24M_CNT_US(us) (24 * us)
#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000))
#define CYCL_32K_CNT_MS(ms) (ms * 32)
......@@ -256,6 +287,12 @@ struct deepsleep_data_s {
#define PWM_DISABLE (0 << 0)
#define PWM_ENABLE (1 << 0)
/* grf reg offset */
#define GRF_DDRC0_CON0 0xe380
#define GRF_DDRC0_CON1 0xe384
#define GRF_DDRC1_CON0 0xe388
#define GRF_DDRC1_CON1 0xe38c
/*
* When system reset in running state, we want the cpus to be reboot
* from maskrom (system reboot),
......
plat/rockchip/rk3399/plat_sip_calls.c
View file @ fe877779
......@@ -29,6 +29,42 @@
#include <plat_sip_calls.h>
#include <rockchip_sip_svc.h>
#include <runtime_svc.h>
#include <dram.h>
#define RK_SIP_DDR_CFG64 0x82000008
#define CONFIG_DRAM_INIT 0x00
#define CONFIG_DRAM_SET_RATE 0x01
#define CONFIG_DRAM_ROUND_RATE 0x02
#define CONFIG_DRAM_SET_AT_SR 0x03
#define CONFIG_DRAM_GET_BW 0x04
#define CONFIG_DRAM_GET_RATE 0x05
#define CONFIG_DRAM_CLR_IRQ 0x06
#define CONFIG_DRAM_SET_PARAM 0x07
uint64_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id)
{
switch (id) {
case CONFIG_DRAM_INIT:
ddr_init();
break;
case CONFIG_DRAM_SET_RATE:
return ddr_set_rate(arg0);
case CONFIG_DRAM_ROUND_RATE:
return ddr_round_rate(arg0);
case CONFIG_DRAM_GET_RATE:
return ddr_get_rate();
case CONFIG_DRAM_CLR_IRQ:
clr_dcf_irq();
break;
case CONFIG_DRAM_SET_PARAM:
dts_timing_receive(arg0, arg1);
break;
default:
break;
}
return 0;
}
uint64_t rockchip_plat_sip_handler(uint32_t smc_fid,
uint64_t x1,
......@@ -40,6 +76,8 @@ uint64_t rockchip_plat_sip_handler(uint32_t smc_fid,
uint64_t flags)
{
switch (smc_fid) {
case RK_SIP_DDR_CFG64:
SMC_RET1(handle, ddr_smc_handler(x1, x2, x3));
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
SMC_RET1(handle, SMC_UNK);
......
plat/rockchip/rk3399/platform.mk
View file @ fe877779
......@@ -40,6 +40,7 @@ PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \
-I${RK_PLAT_SOC}/drivers/pmu/ \
-I${RK_PLAT_SOC}/drivers/pwm/ \
-I${RK_PLAT_SOC}/drivers/soc/ \
-I${RK_PLAT_SOC}/drivers/dram/ \
-I${RK_PLAT_SOC}/include/ \
RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
......@@ -76,6 +77,8 @@ BL31_SOURCES += ${RK_GIC_SOURCES}
${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/pwm/pwm.c \
${RK_PLAT_SOC}/drivers/soc/soc.c
${RK_PLAT_SOC}/drivers/soc/soc.c \
${RK_PLAT_SOC}/drivers/dram/dram.c \
${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c
ENABLE_PLAT_COMPAT := 0
plat/rockchip/rk3399/rk3399_def.h
View file @ fe877779
......@@ -61,6 +61,12 @@
#define PWM_BASE (MMIO_BASE + 0x1420000)
#define PWM_SIZE SIZE_K(64)
#define CIC_BASE (MMIO_BASE + 0x1620000)
#define CIC_SIZE SIZE_K(4)
#define DCF_BASE (MMIO_BASE + 0x16a0000)
#define DCF_SIZE SIZE_K(4)
#define GPIO0_BASE (MMIO_BASE + 0x1720000)
#define GPIO0_SIZE SIZE_K(64)
......@@ -85,12 +91,21 @@
#define STIME_BASE (MMIO_BASE + 0x1860000)
#define STIME_SIZE SIZE_K(64)
#define SRAM_BASE (MMIO_BASE + 0x18c0000)
#define SRAM_SIZE SIZE_K(192)
#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x1a50000)
#define NOC_0_SIZE SIZE_K(192)
#define DDRC0_BASE (MMIO_BASE + 0x1a80000)
#define DDRC0_SIZE SIZE_K(32)
#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x1a84000)
#define NOC_1_SIZE SIZE_K(16)
#define DDRC1_BASE (MMIO_BASE + 0x1a88000)
#define DDRC1_SIZE SIZE_K(32)
#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x1a8c000)
#define NOC_2_SIZE SIZE_K(16)
......@@ -100,6 +115,14 @@
#define CCI500_BASE (MMIO_BASE + 0x1b00000)
#define CCI500_SIZE SIZE_M(1)
#define DDR_PI_OFFSET 0x800
#define DDR_PHY_OFFSET 0x2000
#define DDRC0_PI_BASE (DDRC0_BASE + DDR_PI_OFFSET)
#define DDRC0_PHY_BASE (DDRC0_BASE + DDR_PHY_OFFSET)
#define DDRC1_PI_BASE (DDRC1_BASE + DDR_PI_OFFSET)
#define DDRC1_PHY_BASE (DDRC1_BASE + DDR_PHY_OFFSET)
/* Aggregate of all devices in the first GB */
#define RK3399_DEV_RNG0_BASE MMIO_BASE
#define RK3399_DEV_RNG0_SIZE 0x1d00000
......
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