- 09 Jul, 2019 1 commit
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XiaoDong Huang authored
px30 is a Quad-core soc and Cortex-a53 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Change-Id: I73d55aa978096c078242be921abe0ddca9e8f67e Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
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- 02 Jul, 2019 9 commits
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lauwal01 authored
Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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lauwal01 authored
Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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lauwal01 authored
Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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lauwal01 authored
Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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lauwal01 authored
Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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lauwal01 authored
Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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lauwal01 authored
Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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lauwal01 authored
Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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lauwal01 authored
Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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- 01 Jul, 2019 1 commit
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Soby Mathew authored
Credit to sam.ellis@arm.com for the input to create the list. Change-Id: Id70a8eddc5f2490811bebb278482c61950f10cce Signed-off-by: Soby Mathew <soby.mathew@arm.com>
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- 24 Jun, 2019 1 commit
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John Tsichritzis authored
Change-Id: Ifef4d634b4a34d23f42f61df5e326a1cc05d3844 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 22 Jun, 2019 1 commit
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Peng Donglin authored
Signed-off-by: Peng Donglin <dolinux.peng@gmail.com> Change-Id: I459e7d056735222f6f34e275dbdaf9a389d193fc
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- 17 Jun, 2019 1 commit
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Yann Gautier authored
U-Boot should be compiled with stm32mp15_trusted_defconfig which is supported since tag v2019.07-rc1 with commit [1]. The creation of the U-Boot binary with stm32 header is done at U-Boot compilation step, it is no more required to call the extra command. [1] https://git.denx.de/?p=u-boot.git;a=commit;h=015289580f81 Change-Id: Ia875c22184785fc2e02ad07993a649069cd5ce34 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 12 Jun, 2019 1 commit
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Ambroise Vincent authored
Reference security specific build options from the user guide. Change-Id: I0e1efbf47d914cf3c473104175c702ff1a80eb67 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 10 Jun, 2019 1 commit
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John Tsichritzis authored
Also sort alphabetically the links at the bottom, a couple of them were not sorted. Change-Id: I49a1dbe9e56a36c5fdbace8e4c8b9a5270bc2984 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 06 Jun, 2019 2 commits
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Andre Przywara authored
Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register, which will disable the load-bypass-store feature. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Ambroise Vincent authored
Change-Id: I0d9dbef7041fcf950bcafcdbbc17c72b4dea9e40 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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- 03 Jun, 2019 1 commit
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John Tsichritzis authored
Change-Id: I41ce5323c33a81db13c5cc40de1ac4e221a10cd8 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 31 May, 2019 1 commit
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John Tsichritzis authored
Change-Id: I5cf8c70a304bf5869cbeb12fa8d39171cff48ebd Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 30 May, 2019 2 commits
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Paul Beesley authored
Automatic labelling of document titles is a prerequisite for converting the format of cross-document links. Sphinx will generate (via the enabled extension) a hidden link target for each document title and this can be referred to later, from another page, to link to the target. The plugin options being used require Sphinx >= 2.0.0 so a requirements.txt file has been added. This file is used with the pip package manager for Python so that the correct dependencies are installed. Change-Id: Ic2049db5804aa4a6447608ba4299de958ce0a87d Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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John Tsichritzis authored
Change-Id: Ib021c721652d96f6c06ea18741f19a72bba1d00f Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 28 May, 2019 2 commits
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Ambroise Vincent authored
The workaround is added to the Cortex-A55 cpu specific file. The workaround is disabled by default and have to be explicitly enabled by the platform integrator. Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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John Tsichritzis authored
Change-Id: Ic09e74f22b43fba51ee17cd02b5e1dc5d8e0bb63 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 24 May, 2019 3 commits
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Alexei Fedorov authored
This patch adds the functionality needed for platforms to provide Branch Target Identification (BTI) extension, introduced to AArch64 in Armv8.5-A by adding BTI instruction used to mark valid targets for indirect branches. The patch sets new GP bit [50] to the stage 1 Translation Table Block and Page entries to denote guarded EL3 code pages which will cause processor to trap instructions in protected pages trying to perform an indirect branch to any instruction other than BTI. BTI feature is selected by BRANCH_PROTECTION option which supersedes the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication and is disabled by default. Enabling BTI requires compiler support and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0. The assembly macros and helpers are modified to accommodate the BTI instruction. This is an experimental feature. Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3 is now made as an internal flag and BRANCH_PROTECTION flag should be used instead to enable Pointer Authentication. Note. USE_LIBROM=1 option is currently not supported. Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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John Tsichritzis authored
1) Fix links in "about" page 2) Put back the "contents" page with adjusted links Change-Id: Id09140b91df5cf0a275149801d05d8cfeeda1c6e Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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John Tsichritzis authored
1) Replace references to "Arm Trusted Firmware" with "TF-A" 2) Update issue tracker link Change-Id: I12d827d49f6cc34e46936d7f7ccf44e32b26a0bd Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 22 May, 2019 10 commits
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Paul Beesley authored
The documentation contains plenty of notes and warnings. Enable special rendering of these blocks by converting the note prefix into a .. note:: annotation. Change-Id: I34e26ca6bf313d335672ab6c2645741900338822 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
- Make the list of contributors into an actual list - Use note syntax for the note - Remove the Individuals heading since there are none This file could be considered for removal as it is a legacy document, as its note explains. Change-Id: Idf984bc192af7a0ec367a6642ab99ccccf5df1a8 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
Change-Id: I679d1499376a524bef1cfc33df995b0a719b5ac8 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
Several code blocks do not specify a language for syntax highlighting. This results in Sphinx using a default highlighter which is Python. This patch adds the correct language to each code block that doesn't already specify it. Change-Id: Icce1949aabfdc11a334a42d49edf55fa673cddc3 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
One of the current issues with the documentation is that terms and abbreviations are frequently redefined. For example, we might have a sentence like "... the SCP (System Control Processor) will ...". These definitions might be repeated several times across pages, or even within the same document. Equally, some of these abbreviations are missed and are never expanded. Sphinx provides a :term: keyword that takes some text and, if that text is defined in a glossary document, links to its glossary entry. Using this functionality will prevent repeated definitions and will make the docs more maintainable by using a single definition source. The glossary added in this patch was created from a quick scrub of the source code - there may be missing entries. The SDEI abbreviation was used as an example. Note that a global_substitutions file was created. This file contains the RST 'replace' statements that convert plain text terms into linked terms (by adding the ':term:' keyword to them). An example is: .. |TF-A| replace:: :term:`TF-A` The 'rst_prolog' variable in conf.py is used to inject this list of replacements into each page. Terms must be surrounded with the pipe character to be turned into links - this means that we can still prevent certain terms from being linked if we don't want them to be. Change-Id: I87010ed9cfa4a60011a9b4a431b98cb4bb7baa28 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
These are no longer needed as there will always be a table of contents rendered to the left of every page. Some of these lists can be quite long and, when opening a page, the reader sees nothing but a huge list of contents! After this patch, the document contents are front-and-centre and the contents are nicely rendered in the sidebar without duplication. Change-Id: I444754d548ec91d00f2b04e861de8dde8856aa62 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
Required so that the advisory documents are all valid RST files (with a header) and that they all integrate into the document tree. Change-Id: I68ca2b0b9e648e24b460deb772c471a38518da26 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
The platform port documents are not very standardised right now and they don't integrate properly into the document tree so: 1) Make sure each port has a proper name and title (incl. owner) 2) Correct use of headings, subheadings, etc in each port 3) Resolve any naming conflicts between documents Change-Id: I4c2da6f57172b7f2af3512e766ae9ce3b840b50f Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
Required work to make all documents sit at the correct levels within the document tree and any derived content like the table of contents and the categories in the sidebar. Change-Id: I4885fbe30864a87c8822ee67482b71fb46a8fbc6 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
This patch attempts to standardise the document titles as well as adding titles to documents that were missing one. The aim is to remove needless references to "TF-A" or "Trusted Firmware" in the title of every document and to make sure that the title matches with the document content. Change-Id: I9b93ccf43b5d57e8dc793a5311b8ed7c4dd245cc Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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- 21 May, 2019 3 commits
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Paul Beesley authored
Previously the readme.rst file served as the entrypoint for the documentation. With a Sphinx build the top-level document is set to be index.rst as it contains the primary document index. This patch moves some content from readme.rst into index.rst and splits the license information out into license.rst. Change-Id: I5c50250b81136fe36aa9ceedaae302b44ec11e47 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
This change creates the following directories under docs/ in order to provide a grouping for the content: - components - design - getting_started - perf - process In each of these directories an index.rst file is created and this serves as an index / landing page for each of the groups when the pages are compiled. Proper layout of the top-level table of contents relies on this directory/index structure. Without this patch it is possible to build the documents correctly with Sphinx but the output looks messy because there is no overall hierarchy. Change-Id: I3c9f4443ec98571a56a6edf775f2c8d74d7f429f Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
Add the essentials for supporting a Sphinx documentation build: - A makefile under docs/ to invoke Sphinx with the desired output format - A Sphinx master configuration file (conf.py) - A single, top-level index page (index.rst) - The TF.org logo that is integrated in the the sidebar of the rendered output Change-Id: I85e67e939658638337ca7972936a354878083a25 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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