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  1. 26 Apr, 2018 1 commit
    • Antonio Nino Diaz's avatar
      xlat: Set AP[1] to 1 when it is RES1 · 01c0a38e
      Antonio Nino Diaz authored 
      

According to the ARMv8 ARM issue C.a:

    AP[1] is valid only for stage 1 of a translation regime that can
    support two VA ranges. It is RES 1 when stage 1 translations can
    support only one VA range.

This means that, even though this bit is ignored, it should be set to 1
in the EL3 and EL2 translation regimes.

For translation regimes consisting on EL0 and a higher regime this bit
selects between control at EL0 or at the higher Exception level. The
regimes that support two VA ranges are EL1&0 and EL2&0 (the later one
is only available since ARMv8.1).

This fix has to be applied to both versions of the translation tables
library.

Change-Id: If19aaf588551bac7aeb6e9a686cf0c2068e7c181
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      01c0a38e
  3. 18 Apr, 2018 3 commits
  5. 17 Apr, 2018 2 commits
  7. 16 Apr, 2018 3 commits
  9. 13 Apr, 2018 10 commits
  11. 12 Apr, 2018 4 commits
  13. 11 Apr, 2018 5 commits
  15. 10 Apr, 2018 8 commits
  17. 09 Apr, 2018 4 commits
    • Varun Wadekar's avatar
      lib: xlat_tables_v2: reduce time required to add a mmap region · 0ed32232
      Varun Wadekar authored 
      

The last entry in the mapping table is not necessarily the same as the
end of the table. This patch loops through the table to find the last
entry marker, on every new mmap addition. The memove operation then
has to only move the memory between current entry and the last entry.
For platforms that arrange their MMIO map properly, this opearation
turns out to be a NOP.

The previous implementation added significant overhead per mmap
addition as the memmove operation always moved the difference between
the current mmap entry and the end of the table.

Tested on Tegra platforms and this new approach improves the memory
mapping time by ~75%, thus significantly reducing boot time on some
platforms.

Change-Id: Ie3478fa5942379282ef58bee2085da799137e2ca
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      0ed32232
    • Dimitris Papastamos's avatar
      Merge pull request #1328 from JiafeiPan/upstream-bl2-rom · c39afead
      Dimitris Papastamos authored 
      Add support for BL2 in XIP memory
      c39afead
    • Amit Daniel Kachhap's avatar
      Juno: Increase bl2 max size to fix build when SPD=opteed · 83a2376e
      Amit Daniel Kachhap authored 
      

Building TBBR(SPD=opteed) and non-TBBR TF-A images is breaking for
Juno for different configurations listed below:

* Overflow error of 4096 bytes for rsa algorithm.
* Overflow error of 8192 bytes for ecdsa algorithm.
* Overflow error of 4096 bytes for rsa+ecdsa algorithm.
* Overflow error of 4096 bytes for non-TBBR case.

So this patch increments macro PLAT_ARM_MAX_BL2_SIZE for all the above
cases accordingly.

Change-Id: I75ec6c0a718181d34553fe55437f0496f467683f
Signed-off-by: default avatarAmit Daniel Kachhap <amit.kachhap@arm.com>
      83a2376e
    • Amit Daniel Kachhap's avatar
      DMC500: Add platform support to set system interface count · d12afc8e
      Amit Daniel Kachhap authored 
      

Some low end platforms using DMC500 memory controller do not have
CCI(Cache Coherent Interconnect) interface and only have non-coherent
system interface support. Hence this patch makes the system interface
count configurable from the platforms.

Change-Id: I6d54c90eb72fd18026c6470c1f7fd26c59dc4b9a
Signed-off-by: default avatarAmit Daniel Kachhap <amit.kachhap@arm.com>
      d12afc8e