1. 11 Mar, 2020 1 commit
    • Jeetesh Burman's avatar
      Tegra194: add SE support to generate SHA256 of TZRAM · 029dd14e
      Jeetesh Burman authored
      
      
      The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This
      memory loses power when we enter System Suspend and so its contents are
      stored to TZDRAM, before entry. This opens up an attack vector where the
      TZDRAM contents might be tampered with when we are in the System Suspend
      mode. To mitigate this attack the SE engine calculates the hash of entire
      TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The
      WB0 code will validate the TZDRAM and match the hash with the one in PMC
      scratch.
      
      This patch adds driver for the SE engine, with APIs to calculate the hash
      and store to PMC scratch registers.
      
      Change-Id: I04cc0eb7f54c69d64b6c34fc2ff62e4cfbdd43b2
      Signed-off-by: default avatarJeetesh Burman <jburman@nvidia.com>
      029dd14e
  2. 31 Jan, 2020 1 commit
    • Varun Wadekar's avatar
      Tegra194: se: fix multiple MISRA issues · 8d4107f0
      Varun Wadekar authored
      
      
      This patch fixes violations for the following MISRA rules
      
      * Rule 8.4  "A compatible declaration shall be visible when an object or
                   function with external linkage is defined"
      * Rule 10.1 "Operands shall not be of an inappropriate essential type"
      * Rule 10.6 "Both operands of an operator in which the usual arithmetic
                   conversions are perdormed shall have the same essential type
                   category"
      * Rule 17.7 "The value returned by a function having non-void return
                   type shall be used"
      
      Change-Id: I171ac8340de729fd7be928fa0c0694e9bb8569f0
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      8d4107f0
  3. 23 Jan, 2020 1 commit
  4. 09 Jan, 2020 1 commit
  5. 28 Nov, 2019 1 commit