- 17 Dec, 2019 1 commit
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Heiko Stuebner authored
So far the px30-related ddr security was loading data for regions to secure from a pre-specified memory location and also setting region0 to secure the first megabyte of memory in hard-coded setting (top=0, end=0, meaning 1MB). To make things more explicit and easier to read add a function doing the settings for specified memory areas, like other socs have and also add an assert to make sure any descriptor read from memory does not overlap the TZRAM security in region0 and TEE security in region1. Signed-off-by:Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: I78441875112bf66a62fde5f1789f4e52a78ef95f
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- 27 Nov, 2019 1 commit
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Paul Kocialkowski authored
Add the UART3 base definition for serial output, which is used on some PX30 SoM boards. Signed-off-by:Paul Kocialkowski <paul.kocialkowski@bootlin.com> Change-Id: I8490b15c9f129a33c01cb78bd78675014bc7b015
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- 05 Aug, 2019 1 commit
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Heiko Stuebner authored
The px30 mini-evb can use either uart2 (muxed with the sd-card pins) or uart5 via its pin header for serial output. Uart5 is especially useful when needing to boot from the sd-card, where uart2 obviously is not useable. So add the uart5 constants and it as uart option for the serial-param handler. Signed-off-by:Heiko Stuebner <heiko@sntech.de> Change-Id: Ib88df7a55d761ee104d312c9953a13de3beba1c4
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- 09 Jul, 2019 1 commit
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XiaoDong Huang authored
px30 is a Quad-core soc and Cortex-a53 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Change-Id: I73d55aa978096c078242be921abe0ddca9e8f67e Signed-off-by:XiaoDong Huang <derrick.huang@rock-chips.com>
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