1. 06 Jun, 2019 1 commit
  2. 03 Jun, 2019 3 commits
  3. 31 May, 2019 2 commits
  4. 30 May, 2019 3 commits
  5. 29 May, 2019 4 commits
  6. 28 May, 2019 5 commits
  7. 24 May, 2019 7 commits
    • Paul Beesley's avatar
    • Paul Beesley's avatar
      Merge changes from topic "jts/docs" into integration · c0e9d433
      Paul Beesley authored
      * changes:
        Docs fixes
        Update security documentation
      c0e9d433
    • Alexei Fedorov's avatar
      Add support for Branch Target Identification · 9fc59639
      Alexei Fedorov authored
      
      
      This patch adds the functionality needed for platforms to provide
      Branch Target Identification (BTI) extension, introduced to AArch64
      in Armv8.5-A by adding BTI instruction used to mark valid targets
      for indirect branches. The patch sets new GP bit [50] to the stage 1
      Translation Table Block and Page entries to denote guarded EL3 code
      pages which will cause processor to trap instructions in protected
      pages trying to perform an indirect branch to any instruction other
      than BTI.
      BTI feature is selected by BRANCH_PROTECTION option which supersedes
      the previous ENABLE_PAUTH used for Armv8.3-A Pointer Authentication
      and is disabled by default. Enabling BTI requires compiler support
      and was tested with GCC versions 9.0.0, 9.0.1 and 10.0.0.
      The assembly macros and helpers are modified to accommodate the BTI
      instruction.
      This is an experimental feature.
      Note. The previous ENABLE_PAUTH build option to enable PAuth in EL3
      is now made as an internal flag and BRANCH_PROTECTION flag should be
      used instead to enable Pointer Authentication.
      Note. USE_LIBROM=1 option is currently not supported.
      
      Change-Id: Ifaf4438609b16647dc79468b70cd1f47a623362e
      Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      9fc59639
    • Ambroise Vincent's avatar
      Makefile: Add default warning flags · 00296576
      Ambroise Vincent authored
      
      
      The flags are taken from the different warning levels of the build
      system when they do not generate any error with the current upstreamed
      platforms.
      
      Change-Id: Ia70cff83bedefb6d2f0dd266394ef77fe47e7f65
      Signed-off-by: default avatarAmbroise Vincent <ambroise.vincent@arm.com>
      00296576
    • John Tsichritzis's avatar
      Docs fixes · a16fd37f
      John Tsichritzis authored
      
      
      1) Fix links in "about" page
      2) Put back the "contents" page with adjusted links
      
      Change-Id: Id09140b91df5cf0a275149801d05d8cfeeda1c6e
      Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      a16fd37f
    • John Tsichritzis's avatar
      Update security documentation · 55f14059
      John Tsichritzis authored
      
      
      1) Replace references to "Arm Trusted Firmware" with "TF-A"
      2) Update issue tracker link
      
      Change-Id: I12d827d49f6cc34e46936d7f7ccf44e32b26a0bd
      Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      55f14059
    • John Tsichritzis's avatar
      Beautify "make help" · 7c23126c
      John Tsichritzis authored
      
      
      Changes to make the help text a bit more readable:
      1) The "usage" part is now a one-liner
      2) The supported platforms list is printed separately
      
      Change-Id: I93e48a6cf1d28f0ef9f3db16ce17725e4dff33c9
      Signed-off-by: default avatarJohn Tsichritzis <john.tsichritzis@arm.com>
      7c23126c
  8. 23 May, 2019 4 commits
  9. 22 May, 2019 11 commits
    • Andrew F. Davis's avatar
      ti: k3: common: Set L2 latency on A72 cores · 16a755f3
      Andrew F. Davis authored
      
      
      The Cortex-A72 based cores on K3 platforms can be clocked fast
      enough that an extra latency cycle is needed to ensure correct
      L2 access. Set the latency here for all A72 cores.
      Signed-off-by: default avatarAndrew F. Davis <afd@ti.com>
      Change-Id: Id534316dec1c1f326908efbfd964f219cda7386a
      16a755f3
    • Nishanth Menon's avatar
      ti: k3: common: Add support for J721E · 7c088e71
      Nishanth Menon authored
      
      
      Enable Cortex-A72 support for J721E.
      
      Change-Id: I5bea5fb6ec45d1a9f8f2192d42da2cc03ae0f7ec
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Signed-off-by: default avatarAndrew F. Davis <afd@ti.com>
      7c088e71
    • Paul Beesley's avatar
      doc: Use proper note and warning annotations · e1c5026a
      Paul Beesley authored
      
      
      The documentation contains plenty of notes and warnings. Enable
      special rendering of these blocks by converting the note prefix
      into a .. note:: annotation.
      
      Change-Id: I34e26ca6bf313d335672ab6c2645741900338822
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      e1c5026a
    • Paul Beesley's avatar
      doc: Refactor contributor acknowledgements · f94102ba
      Paul Beesley authored
      
      
      - Make the list of contributors into an actual list
      - Use note syntax for the note
      - Remove the Individuals heading since there are none
      
      This file could be considered for removal as it is a legacy
      document, as its note explains.
      
      Change-Id: Idf984bc192af7a0ec367a6642ab99ccccf5df1a8
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      f94102ba
    • Paul Beesley's avatar
      doc: Reorganise images and update links · a2c320a8
      Paul Beesley authored
      
      
      Change-Id: I679d1499376a524bef1cfc33df995b0a719b5ac8
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      a2c320a8
    • Paul Beesley's avatar
      doc: Set correct syntax highlighting style · 29c02529
      Paul Beesley authored
      
      
      Several code blocks do not specify a language for syntax
      highlighting. This results in Sphinx using a default highlighter
      which is Python.
      
      This patch adds the correct language to each code block that doesn't
      already specify it.
      
      Change-Id: Icce1949aabfdc11a334a42d49edf55fa673cddc3
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      29c02529
    • Paul Beesley's avatar
      doc: Add minimal glossary · 8f62ca7b
      Paul Beesley authored
      
      
      One of the current issues with the documentation is that terms and
      abbreviations are frequently redefined. For example, we might have
      a sentence like "... the SCP (System Control Processor) will ...".
      
      These definitions might be repeated several times across pages, or
      even within the same document. Equally, some of these abbreviations
      are missed and are never expanded.
      
      Sphinx provides a :term: keyword that takes some text and,
      if that text is defined in a glossary document, links to its glossary
      entry. Using this functionality will prevent repeated definitions
      and will make the docs more maintainable by using a single
      definition source.
      
      The glossary added in this patch was created from a quick scrub of
      the source code - there may be missing entries. The SDEI abbreviation
      was used as an example.
      
      Note that a global_substitutions file was created. This file contains
      the RST 'replace' statements that convert plain text terms into linked
      terms (by adding the ':term:' keyword to them). An example is:
      
      .. |TF-A| replace:: :term:`TF-A`
      
      The 'rst_prolog' variable in conf.py is used to inject this list of
      replacements into each page. Terms must be surrounded with the pipe
      character to be turned into links - this means that we can still
      prevent certain terms from being linked if we don't want them to be.
      
      Change-Id: I87010ed9cfa4a60011a9b4a431b98cb4bb7baa28
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      8f62ca7b
    • Paul Beesley's avatar
      doc: Remove per-page contents lists · 57354abb
      Paul Beesley authored
      
      
      These are no longer needed as there will always be a table of contents
      rendered to the left of every page.
      
      Some of these lists can be quite long and, when opening a page, the
      reader sees nothing but a huge list of contents! After this patch,
      the document contents are front-and-centre and the contents are
      nicely rendered in the sidebar without duplication.
      
      Change-Id: I444754d548ec91d00f2b04e861de8dde8856aa62
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      57354abb
    • Paul Beesley's avatar
      doc: Make checkpatch ignore rst files · 1ef35512
      Paul Beesley authored
      
      
      Previously checkpatch was invoked with options to make it ignore
      Markdown (md) files as this was the dominant format for TF-A
      documents. Now that rst is being used everywhere this option needs
      updating.
      
      Change-Id: I59b5a0bcc45d2386df4f880b8d333baef0bbee77
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      1ef35512
    • Paul Beesley's avatar
      doc: Format security advisory titles and headings · 267f8085
      Paul Beesley authored
      
      
      Required so that the advisory documents are all valid RST files (with a
      header) and that they all integrate into the document tree.
      
      Change-Id: I68ca2b0b9e648e24b460deb772c471a38518da26
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      267f8085
    • Paul Beesley's avatar
      doc: Reformat platform port documents · 24dba2b3
      Paul Beesley authored
      
      
      The platform port documents are not very standardised right now and
      they don't integrate properly into the document tree so:
      
      1) Make sure each port has a proper name and title (incl. owner)
      2) Correct use of headings, subheadings, etc in each port
      3) Resolve any naming conflicts between documents
      
      Change-Id: I4c2da6f57172b7f2af3512e766ae9ce3b840b50f
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
      24dba2b3