- 21 Jul, 2020 1 commit
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Vijayenthiran Subramaniam authored
TBBR authentication framework depends on the plat_get_rotpk_info() function to return the pointer to the Root of Trust Public Key (ROTPK) stored in the platform along with its length. Add this function for RD-Daniel Config-XLR platform to support Trusted Board Boot. The function makes use of the wrapper function provided by the arm common trusted board boot function to get the ROTPK hash. Change-Id: I509e2f7e88cc2167e1732a971d71dc131d3d4b01 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
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- 24 Jun, 2020 1 commit
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Manish V Badarkhe authored
Moved BL2 configuration nodes from fw_config to newly created tb_fw_config device tree. fw_config device tree's main usage is to hold properties shared across all BLx images. An example is the "dtb-registry" node, which contains the information about the other device tree configurations (load-address, size). Also, Updated load-address of tb_fw_config which is now located after fw_config in SRAM. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ic398c86a4d822dacd55b5e25fd41d4fe3888d79a
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- 08 Jun, 2020 1 commit
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Manish Pandey authored
As per "include/export/README", TF-A code should never include export headers directly. Instead, it should include a wrapper header that ensures the export header is included in the right manner. "tbbr_img_def_exp.h" is directly included in TF-A code, this patch replaces it with its wrapper header "tbbr_img_def.h". Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I31c1a42e6a7bcac4c396bb17e8548567ecd8147d
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- 30 Apr, 2020 1 commit
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Louis Mayencourt authored
Dynamic configuration properties are fconf properties. Modify the compatible string from "arm,.." to "fconf,.." to reflect this. Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: I85eb75cf877c5f4d3feea3936d4c348ca843bc6c
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- 23 Apr, 2020 1 commit
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Aditya Angadi authored
RD-Daniel Config-XLR platform has four identical chips connected via a high speed coherent CCIX link. Each chip has four Neoverse cores connected via coherent CMN interconnect. Change-Id: I37d1b91f2b6ba08f61c64d0288bc16a429836c08 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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