- 23 Apr, 2019 1 commit
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Yann Gautier authored
A new static function boot_mmc is created to simplify code maintenance of stm32mp_io_setup. Change-Id: I5c416e567e7e174fb1c2b435925a983c9c55fc40 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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- 17 Apr, 2019 3 commits
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Louis Mayencourt authored
Under certain near idle conditions, DSU may miss response transfers on the ACE master or Peripheral port, leading to deadlock. This workaround disables high-level clock gating of the DSU to prevent this. Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Louis Mayencourt authored
Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Louis Mayencourt authored
Under specific conditions, the processor might issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. Set the CPUACTLR.ENDCCASCI bit to 1 to avoid this. Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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- 16 Apr, 2019 1 commit
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John Tsichritzis authored
There is a bug in the shared heap implementation for SGM. Until the bug is solved, the default implementation is used. Change-Id: I010911a3f00ed860f742b14daad1d99b9e7ce711 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 12 Apr, 2019 9 commits
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Antonio Niño Díaz authored
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Antonio Niño Díaz authored
* changes: Mbed TLS: Remove weak heap implementation sgm: Fix bl2 sources
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Antonio Niño Díaz authored
* changes: doc: Clarify cert_create build when USE_TBBR_DEFS=0 plat/sgm: Remove redundant platform_oid.h
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Joel Hutton authored
On Cortex A9 an errata can cause the processor to violate the rules for speculative fetches when the MMU is off but branch prediction has not been disabled. The workaround for this is to execute an Invalidate Entire Branch Prediction Array (BPIALL) followed by a DSB. see:http://arminfo.emea.arm.com/help/topic/com.arm.doc.uan0009d/UAN0009_cortex_a9_errata_r4.pdf for more details. Change-Id: I9146c1fa7563a79f4e15b6251617b9620a587c93 Signed-off-by: Joel Hutton <Joel.Hutton@arm.com>
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Antonio Niño Díaz authored
* changes: rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3 rcar_gen3: drivers: Change to restore timer counter value at resume rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2 rcar_gen3: drivers: ddr: Update DDR setting rev.0.35 rcar_gen3: drivers: qos: change subslot cycle rcar_gen3: drivers: board: Add new board revision for H3ULCB rcar_gen3: plat: Change periodic write DQ training option.
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Antonio Niño Díaz authored
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Antonio Niño Díaz authored
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Ambroise Vincent authored
The implementation of the heap function plat_get_mbedtls_heap() becomes mandatory for platforms supporting TRUSTED_BOARD_BOOT. The shared Mbed TLS heap default weak function implementation is converted to a helper function get_mbedtls_heap_helper() which can be used by the platforms for their own function implementation. Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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John Tsichritzis authored
- Fix broken link to the issue tracker. - Add contents section to make navigation easier throughout the page. - Move the link to documentation contents near the top. Where it was before could be missed and documentation might seem inaccessible. Change-Id: I502e4fc0fd312459cda351d30a8781c221625724 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
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- 11 Apr, 2019 11 commits
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Ambroise Vincent authored
The weak version of plat_get_mbedtls_heap() was being used. Change-Id: I6da331a098dd1af5bb64729d5b914cfb74b8869e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
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Paul Beesley authored
The user guide documentation for the cert_create tool needs to mention that a platform must have a platform_oid.h header file in order to successfully build the cert_create tool when USE_TBBR_DEFS is 0. Change-Id: I77f86a022d207e88a79c97741be3eafbfa0c86f1 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Paul Beesley authored
This file is used when building the cert_create tool without using the 'standard' set of Arm OID values as defined in the TBBR specification (see tbbr_oid.h). This configuration is enabled by setting USE_TBBR_DEFS to 0 during build. At the moment this will fail because the header file included by this file was removed in commit bb41eb7a ("cert: move platform_oid.h to include/tools_share for all platforms"). For the SGM platform this means that there is no current use for this file. Change-Id: I3c82983ada62330f1ab6be6d6c0cf489adabae7b Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Toshiyuki Ogasahara authored
Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: If8918efad0fcbe6f91b66c0c7438406b1d4fb759
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Toshiyuki Ogasahara authored
Changed to save and restore cntpct_el0 using memory mapped register for generic timer when System Suspend and Resume. Reported by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I40fd9f5434c4d52b320cd1d20322b9b8e4e67155
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Yoshifumi Hosoya authored
Very rarely, LPDDR4 power consumption may not decrease In self-refresh mode. This patch fixes the DBSC4 self-refresh mode sequence. Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Kenji Miyazawa <kenji.miyazawa.xt@renesas.com> Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Change-Id: I838fa0892b1caf1ecd3f04538b3427e7d971ef59
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Toshiyuki Ogasahara authored
Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I239f4d9f58d38515a49fa1a22cece48b59710d15
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Chiaki Fujii authored
[IPL/DDR] - Update DDR setting rev.0.35. Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Change-Id: I2b936ca8621ca320cc97353f99240da5f24781f7
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Yoshifumi Hosoya authored
Subslot cycle from 132 to 126 as default setting. Subslot cycle from 264 to 252. [IPL/QoS] - Update H3 Ver.2.0 QoS setting rev.0.21. - Update H3 Ver.3.0 QoS setting rev.0.11. - Update M3 Ver.1.1 QoS setting rev.0.19. - Update M3 Ver.3.0 QoS setting rev.0.02. - Update M3N Ver.1.1 QoS setting rev.0.09. Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I52b1bf880163ce03065dc8933d7f193e45cfd9a5
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Yusuke Goda authored
Board Revision[2:0] 3'b000 Rev1.0 OB 3'b001 Rev1.0 CE 3'b010 Rev2.0 [New] Signed-off-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Change-Id: I0f109cddc95eca78aea34c7149e70f14e2f1620b
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Toshiyuki Ogasahara authored
Periodic write DQ training available as default. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I649cfe538e4e2c7e19145ce7d1938ce4361b2529
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- 10 Apr, 2019 3 commits
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Wei Yu authored
From the hotplug testing on Hikey960, in some case cores fail to become online in the system. When some cores are hotplugged off, if other cores in the same cluster enter into CPU idle states at the meantime, the cluster will be powered off. This introduces the state machine malfunction in the power controller, thus when hotplug on the core afterwards, it fails to boot up the core because the power controller thinks the cluster is powered on. This patch is to avoid race condition between hotplug and idles by preventing cluster power off when some of cores in the cluster are hotplugged off, if all cores in the same cluster are hotplugged off, the cluster can be powered off. Change-Id: Ib2feeb093357c70409a3536cb4f9da9b504fdcbe Signed-off-by: Wei Yu <yuwei3@hisilicon.com> Signed-off-by: Leo Yan <leo.yan@linaro.org>
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Joel Hutton authored
Change-Id: I8b7c7888d09200410e1a1c11a070c94dd8013ea7 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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Joel Hutton authored
On Cortex-A7 an L2 set/way cache maintenance operation can overtake an L1 set/way cache maintenance operation. The mitigation for this is to use a `DSB` instruction before changing cache. The cache cleaning code happens to already be doing this, so only a comment was added. Change-Id: Ia1ffb8ca8b6bbbba422ed6f6818671ef9fe02d90 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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- 09 Apr, 2019 6 commits
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Antonio Niño Díaz authored
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Antonio Niño Díaz authored
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Antonio Niño Díaz authored
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Paul Beesley authored
The spm_sp_get_by_uuid() function is used to look up the secure partition that provides a given service. Within this function, memcmp() is used to compare the service UUIDs but it uses the size of the rdsvc->uuid pointer instead of the size of its content (missing dereference). This means that only a partial comparison is performed as UUIDs are 128 bits in length and rdsvc->uuid is a uint32_t typed pointer. Instead, use the size of the array pointed to by the svc_uuid parameter, which will be the full 128 bits, for the comparison. Change-Id: I258fb0cca3bf19f97b8f2a4c133981647cd050e4 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Antonio Niño Díaz authored
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Joel Hutton authored
Change-Id: I0cb9f0db1ef3491f55c038a10db5a88d37e89697 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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- 08 Apr, 2019 6 commits
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Antonio Niño Díaz authored
* changes: Document changes to auth-framework cot-desc: optimise memory further Reduce memory needed for CoT description
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Alexei Fedorov authored
Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Joel Hutton authored
The data structures in the auth-framework were changed by the previous patch, and need to be updated. Change-Id: Icfad2ac688d03d32aa93e45f930a375abbc164a9 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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Joel Hutton authored
This changes the auth_img_desc_t struct to have pointers to struct arrays instead of struct arrays. This saves memory as many of these were never used, and can be NULL pointers. Note the memory savings are only when these arrays are not initialised, as it is assumed these arrays are fixed length. A possible future optimisation could allow for variable length. memory diff: bl1: bl2: text text -12 -12 bss bss -1463 0 data data -56 -48 rodata rodata -5688 -2592 total total -7419 -2652 Change-Id: I8f9bdedf75048b8867f40c56381e3a6dc6402bcc Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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Joel Hutton authored
When Trusted Board Boot is enabled, we need to specify the Chain of Trust (CoT) of the BL1 and BL2 images. A CoT consists of an array of image descriptors. The authentication module assumes that each image descriptor in this array is indexed by its unique image identifier. For example, the Trusted Boot Firmware Certificate has to be at index [TRUSTED_BOOT_FW_CERT_ID]. Unique image identifiers may not necessarily be consecutive. Also, a given BL image might not use all image descriptors. For example, BL1 does not need any of the descriptors related to BL31. As a result, the CoT array might contain holes, which unnecessarily takes up space in the BL binary. Using pointers to auth_img_desc_t structs (rather than structs themselves) means these unused elements only use 1 pointer worth of space, rather than one struct worth of space. This patch also changes the code which accesses this array to reflect the change to pointers. Image descriptors not needed in BL1 or BL2 respectively are also ifdef'd out in this patch. For example, verifying the BL31 image is the responsibility of BL2 so BL1 does not need any of the data structures describing BL31. memory diff: bl1: bl2: text text -20 -20 bss bss -1463 0 data data -256 -48 rodata rodata -5240 -1952 total total -6979 -2020 Change-Id: I163668b174dc2b9bbb183acec817f2126864aaad Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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Antonio Niño Díaz authored
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