- 18 Mar, 2021 2 commits
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Madhukar Pappireddy authored
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Madhukar Pappireddy authored
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- 17 Mar, 2021 2 commits
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Sandrine Bailleux authored
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deqi.hu authored
1.Since in mmc_init, the most of mmc_device_info passed in are temporary variables. In order to avoid referencing the released space on the stack when maybe MISUSED, it`s better to use global variables to store mmc_device_info in mmc.c 2.Delete redundant; Signed-off-by: deqi.hu@siengine.com Change-Id: I51ae90e7f878b19b4963508b3f7ec66339015ebc
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- 16 Mar, 2021 1 commit
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Olivier Deprez authored
* changes: SPM: declare third cactus instance as UP SP SPMD: lock the g_spmd_pm structure FF-A: implement FFA_SECONDARY_EP_REGISTER
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- 15 Mar, 2021 4 commits
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Madhukar Pappireddy authored
* changes: plat: tc0: add matterhorn_elp_arm library to tc0 cpus: add Matterhorn ELP ARM cpu library
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Olivier Deprez authored
The FF-A v1.0 spec allows two configurations for the number of EC/vCPU instantiated in a Secure Partition: -A MultiProcessor (MP) SP instantiates as many ECs as the number of PEs. An EC is pinned to a corresponding physical CPU. -An UniProcessor (UP) SP instantiates a single EC. The EC is migrated to the physical CPU from which the FF-A call is originating. This change permits exercising the latter case within the TF-A-tests framework. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I7fae0e7b873f349b34e57de5cea496210123aea0
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Olivier Deprez authored
Add a lock and spin lock/unlock calls when accessing the fields of the SPMD PM structure. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I9bab705564dc1ba003c29512b1f9be5f126fbb0d
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Olivier Deprez authored
Remove the former impdef SPMD service for SPMC entry point registration. Replace with FFA_SECONDARY_EP_REGISTER ABI providing a single entry point address into the SPMC for primary and secondary cold boot. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I067adeec25fc12cdae90c15a616903b4ac4d4d83
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- 12 Mar, 2021 1 commit
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Sandrine Bailleux authored
* changes: plat/arm: Remove ARM_LINUX_KERNEL_AS_BL33 relying on RESET_TO_BL31 plat/arm: Always allow ARM_LINUX_KERNEL_AS_BL33
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- 10 Mar, 2021 4 commits
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Usama Arif authored
Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: Ie199c60553477c43d1665548ae78cdfd1aa7ffcf
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Usama Arif authored
Change-Id: Ie1acde619a5b21e09717c0e80befb6d53fd16607 Signed-off-by: Usama Arif <usama.arif@arm.com>
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Madhukar Pappireddy authored
* changes: qemu/qemu_sbsa: fix memory type of secure NOR flash qemu/qemu_sbsa: spm_mm supports 512 cores
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Madhukar Pappireddy authored
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- 09 Mar, 2021 2 commits
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Manish Pandey authored
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Heiko Stuebner authored
Compiling BL31 for the Rockchip platform now produces a message about the deprecation of gic_common.c. Follow the advice and use include gicv2.mk instead. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: I396b977d57975dba27cfed801ad5264bbbde2b5e
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- 08 Mar, 2021 3 commits
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Madhukar Pappireddy authored
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Yann Gautier authored
When bit 20 of TZC400 Fail control register [1] is set to 1, it means Privileged access, the macros FAIL_CONTROL_PRIV_PRIV and FAIL_CONTROL_PRIV_UNPRIV are then updated to reflect this. [1] https://developer.arm.com/documentation/ddi0504/c/programmers-model/register-descriptions/fail-control-register?lang=en Change-Id: I01e522fded5cf66c9827293ddcf543c79f9e509e Signed-off-by: Yann Gautier <yann.gautier@st.com>
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Roger Lu authored
The case for value "VCOREFS_SMC_CMD_INIT" is not terminated by a "break" statement. Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: I56cc7c1648e101c0da6e77e592e6edbd5d37724e
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- 05 Mar, 2021 3 commits
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Mark Dykes authored
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Tony Xie authored
when updata routing of an SDEI event, if the registration flags is SDEI_REGF_RM_PE, need to updata the affinity of shared event. Signed-off-by: Tony Xie <tony.xie@rock-chips.com> Change-Id: Ie5d7cc4199253f6af1c28b407f712caac3092d06
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Manish Pandey authored
* changes: drivers/gicv3: also shift eSPI register offset in GICD_OFFSET_64() drivers/gicv3: add debug log for maximum INTID of SPI and eSPI drivers/gicv3: limit SPI ID to avoid misjudgement in GICD_OFFSET() drivers/gicv3: fix logical issue for num_eints drivers/gicv3: fix potential GICD context override with ESPI enabled drivers/gicv3: use mpidr to probe GICR for current CPU
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- 04 Mar, 2021 2 commits
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Madhukar Pappireddy authored
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Pali Rohár authored
Make the aarch64's el3_panic() function print a newline character after PC address, otherwise the output can get mangled in one line with output from other firmware. Here is an example of how the output of el3_panic() got mangled with Linux' console output: ERROR: Unhandled External Abort received on 0x80000001 at EL3! ERROR: exception reason=1 syndrome=0x92000210 PANIC at PC : 0x0000000004027400[13438.473133] rcu: INFO: rcu_sched detected stalls on CPUs/tasks: [13438.479255] rcu: 1-...0: (4 ticks this GP) idle=35e/1/0x4000000000000000 softirq=146459/146459 fqs=2625 The aarch32 version of this function already does this. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I9f0d032c6cd1e2be7a1837f9c8e8244d30633993
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- 03 Mar, 2021 9 commits
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Mark Dykes authored
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Madhukar Pappireddy authored
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Madhukar Pappireddy authored
* changes: mediatek: mt8192: Add Vcore DVFS driver mediatek: mt8192: Add SPM suspend driver mediatek: mt8192: supports mcusys off when system suspend mediatek: mt8192: Add lpm driver
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Xi Chen authored
1 Only enable domain D0 and D1:PCIe access 0xC0000000~0xC4000000; 2 Only enable domain D0 and D3(SCP) access 0x50000000~0x51400000; Signed-off-by: Xi Chen <xixi.chen@mediatek.com> Change-Id: Ic4f9e6d85bfd1cebdb24ffc1d14309c89c103b2a
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Roger Lu authored
Change-Id: I4bd4612a7c7727a5be70957ae940e5f51c7ca5e6 Signed-off-by: Roger Lu <roger.lu@mediatek.com>
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Roger Lu authored
Supports dram/mainpll/26m off when system suspend Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: Id13a06d4132f00fb60066de75920ecac18306e32
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Roger Lu authored
Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: I0ea7f61085ea9ba26c580107ef0cb9940a25f5e2
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Roger Lu authored
Low Power Management (LPM) helps find a suitable configuration for letting system entering idle or suspend with the most resources off. Change-Id: Ie6a7063b666cf338cff5bc972c9025b26de482eb Signed-off-by: Roger Lu <roger.lu@mediatek.com>
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Venkatesh Yadav Abbarapu authored
Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are 0x7d, 0x78 and 0x7f. Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Change-Id: I566f707116d83475de7c87a6004ca96bf7bccebe
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- 02 Mar, 2021 6 commits
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Madhukar Pappireddy authored
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bipin.ravi authored
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Manish Pandey authored
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sah01 authored
Signed-off-by: sah01 <sahil@arm.com> Change-Id: Ic11d739c0bf2076354716cc06fbe25e9000a21e7
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Manish Pandey authored
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Tejas Patel authored
Return timeout error if, IPI is not acked in specified timeout. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Change-Id: I27be3d4d4eb5bc57f6a84c839e2586278c0aec19
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- 01 Mar, 2021 1 commit
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johpow01 authored
Add basic support for Makalu CPU. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I4e85d425eedea499adf585eb8ab548931185043d
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