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  1. 04 Oct, 2020 2 commits
  3. 11 Aug, 2020 1 commit
    • Stefan Chulski's avatar
      plat: marvell: ap807: implement workaround for errata-id 3033912 · 5e4c97d0
      Stefan Chulski authored 
      

ERRATA ID: RES-3033912 - Internal Address Space Init state causes
a hang upon accesses to [0xf070_0000, 0xf07f_ffff]
Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to
split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and
[0x80_0000, 0xff_ffff] that cause accesses to the segment of
[0xf070_0000, 0xf07f_ffff] to act as RAZWI. Reuse common
work-around code for both AP806 and AP807.

Change-Id: Ia91a4802d02917d1682faa0c81571093d1687d97
Signed-off-by: default avatarStefan Chulski <stefanc@marvell.com>
      5e4c97d0
  5. 10 Jul, 2020 5 commits
  7. 19 Jun, 2020 5 commits
  9. 06 Jun, 2020 8 commits
  11. 03 Jun, 2020 1 commit
  13. 25 Feb, 2020 1 commit
  15. 30 Jan, 2020 1 commit
    • Grzegorz Jaszczyk's avatar
      plat: marvell: armada: add support for loading MG CM3 images · 81646055
      Grzegorz Jaszczyk authored 
      

In order to access MG SRAM, the amb bridge needs to be configured which is
done in bl2 platform init.

For MG CM3, the image is only loaded to its SRAM and the CM3 itself is
left in reset. It is because the next stage bootloader (e.g. u-boot)
will trigger action which will take it out of reset when needed. This
can happen e.g. when appropriate device-tree setup (which has enabled
802.3 auto-neg) will be chosen. In other cases the MG CM3 should not be
running.

Change-Id: I816ea14e3a7174eace068ec44e3cc09998d0337e
Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
      81646055
  17. 11 Dec, 2019 2 commits
    • Marek Behún's avatar
      drivers: marvell: comphy-a3700: support SGMII COMPHY power off · 629dd61f
      Marek Behún authored 
      

Add support for powering off the SGMII COMPHY (on lanes 0 and 1).
This is needed sometimes on Turris Mox when using KEXEC.

There is also another benefit of a little energy saving when the given
network interface is down.
Signed-off-by: default avatarMarek Behún <marek.behun@nic.cz>
Change-Id: I55ae0fe3627e7cc0f65c78a00771939d8bf5399f
      629dd61f
    • Marek Behún's avatar
      drivers: marvell: comphy-a3700: fix USB3 powering on when on lane 2 · b662232d
      Marek Behún authored 
      

When USB3 is on lane 2 and indirect register access is used, the polling
at the end of the mvebu_a3700_comphy_usb3_power_on function is
incorrect.

The LOOPBACK_REG0 register should not be used at all. Instead we have to
write the LANE_STATUS1 register address (with offset
USB3PHY_LANE2_REG_BASE_OFFSET) into the indirect address register and
then we should poll indirect data register.

This fixes problems on Turris Mox, which uses lane 2 for USB3.
Signed-off-by: default avatarMarek Behún <marek.behun@nic.cz>
Change-Id: I968b0cccee5ddbe10a2b5614e52e52d87682aacd
      b662232d
  19. 11 Jul, 2019 1 commit
  21. 03 Apr, 2019 1 commit
  23. 04 Jan, 2019 1 commit
    • Antonio Nino Diaz's avatar
      Sanitise includes across codebase · 09d40e0e
      Antonio Nino Diaz authored 
      Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca339

 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      09d40e0e
  25. 04 Dec, 2018 3 commits
  27. 15 Nov, 2018 1 commit
  29. 08 Nov, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Standardise header guards across codebase · c3cf06f1
      Antonio Nino Diaz authored 
      

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      c3cf06f1
  31. 22 Oct, 2018 2 commits
  33. 18 Oct, 2018 1 commit
    • Grzegorz Jaszczyk's avatar
      mvebu: cp110: introduce COMPHY porting layer · 42a29337
      Grzegorz Jaszczyk authored 
      

Some of COMPHY parameters depends on the hw connection between the SoC
and the PHY, which can vary on different boards e.g. due to different
wires length. Define the "porting layer" with some defaults
parameters. It ease updating static values which needs to be updated due
to board differences, which are now grouped in one place.

Example porting layer for a8k-db is under:
plat/marvell/a8k/a80x0/board/phy-porting-layer.h

If for some boards parameters are not defined (missing
phy-porting-layer.h), the default values are used
(drivers/marvell/comphy/phy-default-porting-layer.h)
and the following compilation warning is show:
"Using default comphy params - you may need to suit them to your board".

The common COMPHY driver code is extracted in order to be shared with
future COMPHY driver for A3700 SoC platforms
Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: default avatarIgal Liberman <igall@marvell.com>
Signed-off-by: default avatarKonstantin Porotchkin <kostap@marvell.com>
      42a29337
  35. 19 Sep, 2018 1 commit
    • Andre Przywara's avatar
      drivers: i2c: mentor: move platform code into header files · dfc0fb27
      Andre Przywara authored 
      

At the moment we have two I2C stub drivers (for the Allwinner and the
Marvell platform), which #include the actual .c driver file.
Change this into the more usual design, by renaming and moving the stub
drivers into platform specific header files and including these from the
actual driver file. The platform specific include directories make sure
the driver picks up the right header automatically.
Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
      dfc0fb27
  37. 05 Sep, 2018 2 commits
    • Icenowy Zheng's avatar
      drivers: mentor: extract MI2CV driver from Marvell driver · 7e4d5620
      Icenowy Zheng authored 
      

The Marvell A8K SoCs use the MI2CV IP core from Mentor Graphics, which
is also used by Allwinner.

As Mentor Graphics allows a lot of customization, the MI2CV in the two
SoC families are not compatible, and driver modifications are needed.

Extract the common code to a MI2CV driver.
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
      7e4d5620
    • Icenowy Zheng's avatar
      marvell: drivers: use anonymous union in I2C driver · f348c351
      Icenowy Zheng authored 
      

The I2C controller found in Marvell A8K SoCs (and some older SoCs) mux
status and baudrate registers into the same address, however, it's a
vendor customization, and the original IP core by Mentor Graphics uses
two different addresses for the two registers.

Use anonymous union in the driver, in order to ease code sharing for
other SoC vendors that use this IP core (Allwinner SoCs that are newly
introduced to mainline ATF use this core).
Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
      f348c351