1. 08 Jun, 2020 6 commits
  2. 05 Jun, 2020 3 commits
  3. 04 Jun, 2020 2 commits
  4. 03 Jun, 2020 15 commits
  5. 02 Jun, 2020 3 commits
    • Jimmy Brisson's avatar
      Enable ARMv8.6-ECV Self-Synch when booting to EL2 · 29d0ee54
      Jimmy Brisson authored
      
      
      Enhanced Counter Virtualization, ECV, is an architecture extension introduced
      in ARMv8.6. This extension allows the hypervisor, at EL2, to setup
      self-synchronizing views of the timers for it's EL1 Guests. This patch pokes the
      control register to enable this extension when booting a hypervisor at EL2.
      
      Change-Id: I4e929ecdf400cea17eff1de5cf8704aa7e40973d
      Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      29d0ee54
    • Jimmy Brisson's avatar
      Enable ARMv8.6-FGT when booting to EL2 · 110ee433
      Jimmy Brisson authored
      
      
      The Fine Grained Traps (FGT) architecture extension was added to aarch64 in
      ARMv8.6. This extension primarily allows hypervisors, at EL2, to trap specific
      instructions in a more fine grained manner, with an enable bit for each
      instruction. This patch adds support for this extension by enabling the
      extension when booting an hypervisor at EL2.
      
      Change-Id: Idb9013ed118b6a1b7b76287237096de992ca4da3
      Signed-off-by: default avatarJimmy Brisson <jimmy.brisson@arm.com>
      110ee433
    • Masahisa Kojima's avatar
      xlat_tables_v2: add base table section name parameter for spm_mm · 0922e481
      Masahisa Kojima authored
      Core spm_mm code expects the translation tables are located in the
      inner & outer WBWA & shareable memory.
      REGISTER_XLAT_CONTEXT2 macro is used to specify the translation
      table section in spm_mm.
      
      In the commit 363830df
      
       (xlat_tables_v2: merge
      REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}), REGISTER_XLAT_CONTEXT2
      macro explicitly specifies the base xlat table goes into .bss by default.
      This change affects the existing SynQuacer spm_mm implementation.
      plat/socionext/synquacer/include/plat.ld.S linker script intends to
      locate ".bss.sp_base_xlat_table" into "sp_xlat_table" section,
      but this implementation is no longer available.
      
      This patch adds the base table section name parameter for
      REGISTER_XLAT_CONTEXT2 so that platform can specify the
      inner & outer WBWA & shareable memory for spm_mm base xlat table.
      If PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME is not defined, base xlat table
      goes into .bss by default, the result is same as before.
      
      Change-Id: Ie0e1a235e5bd4288dc376f582d6c44c5df6d31b2
      Signed-off-by: default avatarMasahisa Kojima <masahisa.kojima@linaro.org>
      0922e481
  6. 01 Jun, 2020 6 commits
  7. 31 May, 2020 1 commit
    • Alexei Fedorov's avatar
      TF-A: Fix BL31 linker script error · 34dd1e96
      Alexei Fedorov authored
      
      
      The patch fixes BL31 linker script error
      "Init code ends past the end of the stacks"
      for platforms with number of CPUs less than 4,
      which is caused by __STACKS_END__ address being
      lower than __INIT_CODE_END__.
      The modified BL31 linker script detects such cases
      and increases the total amount of stack memory,
      setting __STACKS_END__ = __INIT_CODE_END__, and
      CPUs' stacks are calculated by BL31 'plat_get_my_stack'
      function accordingly. For platforms with more than 4 CPUs
      and __INIT_CODE_END__ < __STACKS_END__ stack memory does not
      increase and allocated CPUs' stacks match the existing
      implementation.
      The patch removes exclusion of PSCI initialization
      functions from the reclaimed .init section in
      'arm_reclaim_init.ld.S' script, which increases the
      size of reclaimed memory region.
      
      Change-Id: I927773e00dd84e1ffe72f9ee534f4f2fc7b6153c
      Signed-off-by: default avatarAlexei Fedorov <Alexei.Fedorov@arm.com>
      34dd1e96
  8. 30 May, 2020 1 commit
  9. 29 May, 2020 1 commit
  10. 28 May, 2020 2 commits