- 08 Jun, 2020 6 commits
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Manish Pandey authored
* changes: plat: intel: Additional instruction required to enable global timer plat: intel: Fix CCU initialization for Agilex plat: intel: Add FPGAINTF configuration to when configuring pinmux plat: intel: set DRVSEL and SMPLSEL for DWMMC plat: intel: Fix clock configuration bugs
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Tien Hock Loh authored
There are additional instruction needed to enable the global timer. This fixes the global timer initialization Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Idaf2d23359aacc417e2b7d8cdf1688b5cd17ca98
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Tien Hock Loh authored
The CCU initialization loop uses the wrong units, this fixes that. This also fixes snoop filter register set bits should be used instead of overwriting the register Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Ia15eeeae5569b00ad84120182170d353ee221b31
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Tien Hock Loh authored
FPGAINTF wasn't enabled when configuring pinmux. This fixes the issue. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: I5a6aacd504901b8f7327b2f4854b8a77d0c37019
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Tien Hock Loh authored
DRVSEL and SMPLSEL needs to be set so that it can properly go into full speed mode. This needs to be done in EL3 as the registers are secured. Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
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Tien Hock Loh authored
This fixes a few issues on the Agilex clock configuration: - Set clock manager into boot mode before configuring clock - Fix wrong divisor used when calculating vcocalib - PLL sync configuration should be read and then written - Wait PLL lock after PLL sync configuration is done - Clear interrupt bits instead of set interrupt bits after configuration Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: I54c1dc5fe9b102e3bbc1237a92d8471173b8af70
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- 05 Jun, 2020 3 commits
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Madhukar Pappireddy authored
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Madhukar Pappireddy authored
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Heiko Stuebner authored
Current value is 16, count the MAP_REGION calls gets us at least 17, so increase the max value to 20 to have a bit of a margin. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: I93d0324f3d483758366e758f8f663545d365e03f
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- 04 Jun, 2020 2 commits
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Lauren Wehrmeister authored
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Manish Pandey authored
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- 03 Jun, 2020 15 commits
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Manish Pandey authored
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Madhukar Pappireddy authored
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Madhukar Pappireddy authored
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Etienne Carriere authored
Fix etzpc node location in stm32mp157c DTSI file as requested during the patch review. The comment was addressed then fixup change discarded while rebasing. Change-Id: Ie53531fec7da224de0b86c968a66aec441bfc25d Fixes: 627298d4 ("dts: stm32mp157c: add etzpc node") Reported-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Manish Pandey authored
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Masahisa Kojima authored
64KB was not enouth to handle fdt, bl2 shows following error message. "ERROR: Invalid Device Tree at 0x10000000000: error -3" This patch increases the size to 1MB to address above error. Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I0726a0cea95087175451da0dba7410acd27df808
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Manish Pandey authored
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Manish Pandey authored
* changes: plat/stm32mp1: sp_min relies on etzpc driver dts: stm32mp157c: add etzpc node drivers: introduce ST ETZPC driver
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Manish Pandey authored
* changes: Enable ARMv8.6-ECV Self-Synch when booting to EL2 Enable ARMv8.6-FGT when booting to EL2
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Etienne Carriere authored
Use ETZPC driver to configure secure aware interfaces to assign them to non-secure world. Sp_min also configures BootROM resources and SYSRAM to assign both to secure world only. Define stm32mp15 SoC identifiers for the platform specific DECPROT instances. Change-Id: I3bec9f47b04bcba3929e4df886ddb1d5ff843089 Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
Add a node for the ETZPC device so that driver initializes during stm32mp15* boot sequence. Change-Id: I84bf10572e5df7b8f450163c79bcfe6956fc838f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Etienne Carriere authored
ETZPC stands for Extended TrustZone Protection Controller. It is a resource conditional access device. It is mainly based on Arm TZPC. ST ETZPC exposes memory mapped DECPROT cells to set access permissions to SoC peripheral interfaces as I2C, SPI, DDR controllers, and some of the SoC internal memories. ST ETZPC exposes memory mapped TZMA cells to set access permissions to some SoC internal memories. Change-Id: I47ce20ffcfb55306dab923153b71e1bcbe2a5570 Co-developed-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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Marcin Wojtas authored
This patch enables the stream ID for the SD/MMC controllers via dedicated unit register. Thanks to this change it is possible to configure properly the IOMMU in OS and use the SD/MMC interface in a guest Virtual Machine. Change-Id: I99cbd2c9882eb558ba01405d3d8a3e969f06e082 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Tomasz Nowicki <tn@semihalf.com>
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Manish Pandey authored
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Marcin Wojtas authored
BL31_CACHE_DISABLE flag was introduced as a work-around for the older SoC revisions. Since it is not relevant in the newest versions, toggle it to be disabled by default. One can still specify it by adding 'BL31_CACHE_DISABLE=1' string to the build command. Change-Id: I11b52dade3ff7f8ee643b8078c6e447c45946570 Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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- 02 Jun, 2020 3 commits
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Jimmy Brisson authored
Enhanced Counter Virtualization, ECV, is an architecture extension introduced in ARMv8.6. This extension allows the hypervisor, at EL2, to setup self-synchronizing views of the timers for it's EL1 Guests. This patch pokes the control register to enable this extension when booting a hypervisor at EL2. Change-Id: I4e929ecdf400cea17eff1de5cf8704aa7e40973d Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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Jimmy Brisson authored
The Fine Grained Traps (FGT) architecture extension was added to aarch64 in ARMv8.6. This extension primarily allows hypervisors, at EL2, to trap specific instructions in a more fine grained manner, with an enable bit for each instruction. This patch adds support for this extension by enabling the extension when booting an hypervisor at EL2. Change-Id: Idb9013ed118b6a1b7b76287237096de992ca4da3 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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Masahisa Kojima authored
Core spm_mm code expects the translation tables are located in the inner & outer WBWA & shareable memory. REGISTER_XLAT_CONTEXT2 macro is used to specify the translation table section in spm_mm. In the commit 363830df (xlat_tables_v2: merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}), REGISTER_XLAT_CONTEXT2 macro explicitly specifies the base xlat table goes into .bss by default. This change affects the existing SynQuacer spm_mm implementation. plat/socionext/synquacer/include/plat.ld.S linker script intends to locate ".bss.sp_base_xlat_table" into "sp_xlat_table" section, but this implementation is no longer available. This patch adds the base table section name parameter for REGISTER_XLAT_CONTEXT2 so that platform can specify the inner & outer WBWA & shareable memory for spm_mm base xlat table. If PLAT_SP_IMAGE_BASE_XLAT_SECTION_NAME is not defined, base xlat table goes into .bss by default, the result is same as before. Change-Id: Ie0e1a235e5bd4288dc376f582d6c44c5df6d31b2 Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
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- 01 Jun, 2020 6 commits
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Jimmy Brisson authored
Change-Id: I89b90cbdfc8f2aa898b4f3676a4764f060f8e138 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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Jimmy Brisson authored
This should allow git to easily track file moves Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com> Change-Id: I1592cf39a4f94209c560dc6d1a8bc1bfb21d8327
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Jan Kiszka authored
This allows to build for k3-based boards that use a different UART as console, such as the IOT2050 which requires K3_USART=1. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Change-Id: I7171f86c3cabae2c575b8fbeecef839b48bd109b
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Mark Dykes authored
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Mark Dykes authored
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Etienne Carriere authored
Changes stm32mp1 reset driver to API to add a timeout argument to stm32mp_reset_assert() and stm32mp_reset_deassert() and a return value. With a supplied timeout, the functions wait the target reset state is reached before returning. With a timeout of zero, the functions simply load target reset state in SoC interface and return without waiting. Helper functions stm32mp_reset_set() and stm32mp_reset_release() use a zero timeout and return without a return code. This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c accordingly without any functional change. functional change. Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
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- 31 May, 2020 1 commit
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Alexei Fedorov authored
The patch fixes BL31 linker script error "Init code ends past the end of the stacks" for platforms with number of CPUs less than 4, which is caused by __STACKS_END__ address being lower than __INIT_CODE_END__. The modified BL31 linker script detects such cases and increases the total amount of stack memory, setting __STACKS_END__ = __INIT_CODE_END__, and CPUs' stacks are calculated by BL31 'plat_get_my_stack' function accordingly. For platforms with more than 4 CPUs and __INIT_CODE_END__ < __STACKS_END__ stack memory does not increase and allocated CPUs' stacks match the existing implementation. The patch removes exclusion of PSCI initialization functions from the reclaimed .init section in 'arm_reclaim_init.ld.S' script, which increases the size of reclaimed memory region. Change-Id: I927773e00dd84e1ffe72f9ee534f4f2fc7b6153c Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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- 30 May, 2020 1 commit
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joanna.farley authored
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- 29 May, 2020 1 commit
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Sandrine Bailleux authored
As per the trustedfirmware.org Project Maintenance Process [1], the current maintainers of the TF-A project have nominated some contributors to become maintainers themselves. List them in the maintainers.rst file to make this official. [1] https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/ Change-Id: Id4e3cfd12a9074f4e255087fa5dd6fa5f902845f Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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- 28 May, 2020 2 commits
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Mark Dykes authored
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Mark Dykes authored
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