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  1. 04 May, 2018 2 commits
    • Jeenu Viswambharan's avatar
      AArch64: Introduce RAS handling · 14c6016a
      Jeenu Viswambharan authored 
      

RAS extensions are mandatory for ARMv8.2 CPUs, but are also optional
extensions to base ARMv8.0 architecture.

This patch adds build system support to enable RAS features in ARM
Trusted Firmware. A boolean build option RAS_EXTENSION is introduced for
this.

With RAS_EXTENSION, an Exception Synchronization Barrier (ESB) is
inserted at all EL3 vector entry and exit. ESBs will synchronize pending
external aborts before entering EL3, and therefore will contain and
attribute errors to lower EL execution. Any errors thus synchronized are
detected via. DISR_EL1 register.

When RAS_EXTENSION is set to 1, HANDLE_EL3_EA_FIRST must also be set to 1.

Change-Id: I38a19d84014d4d8af688bd81d61ba582c039383a
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      14c6016a
    • Jeenu Viswambharan's avatar
      AArch64: Refactor GP register restore to separate function · ef653d93
      Jeenu Viswambharan authored 
      

At present, the function that restores general purpose registers also
does ERET. Refactor the restore code to restore general purpose
registers without ERET to complement the save function.

The macro save_x18_to_x29_sp_el0 was used only once, and is therefore
removed, and its contents expanded inline for readability.

No functional changes, but with this patch:

  - The SMC return path will incur an branch-return and an additional
    register load.

  - The unknown SMC path restores registers x0 to x3.

Change-Id: I7a1a63e17f34f9cde810685d70a0ad13ca3b7c50
Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
      ef653d93
  3. 26 Apr, 2018 1 commit
    • Antonio Nino Diaz's avatar
      xlat: Set AP[1] to 1 when it is RES1 · 01c0a38e
      Antonio Nino Diaz authored 
      

According to the ARMv8 ARM issue C.a:

    AP[1] is valid only for stage 1 of a translation regime that can
    support two VA ranges. It is RES 1 when stage 1 translations can
    support only one VA range.

This means that, even though this bit is ignored, it should be set to 1
in the EL3 and EL2 translation regimes.

For translation regimes consisting on EL0 and a higher regime this bit
selects between control at EL0 or at the higher Exception level. The
regimes that support two VA ranges are EL1&0 and EL2&0 (the later one
is only available since ARMv8.1).

This fix has to be applied to both versions of the translation tables
library.

Change-Id: If19aaf588551bac7aeb6e9a686cf0c2068e7c181
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      01c0a38e
  5. 17 Apr, 2018 1 commit
  7. 12 Apr, 2018 2 commits
  9. 09 Apr, 2018 1 commit
    • Varun Wadekar's avatar
      lib: xlat_tables_v2: reduce time required to add a mmap region · 0ed32232
      Varun Wadekar authored 
      

The last entry in the mapping table is not necessarily the same as the
end of the table. This patch loops through the table to find the last
entry marker, on every new mmap addition. The memove operation then
has to only move the memory between current entry and the last entry.
For platforms that arrange their MMIO map properly, this opearation
turns out to be a NOP.

The previous implementation added significant overhead per mmap
addition as the memmove operation always moved the difference between
the current mmap entry and the end of the table.

Tested on Tegra platforms and this new approach improves the memory
mapping time by ~75%, thus significantly reducing boot time on some
platforms.

Change-Id: Ie3478fa5942379282ef58bee2085da799137e2ca
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
      0ed32232
  11. 27 Mar, 2018 2 commits
    • Jonathan Wright's avatar
      psci: initialize array fully to comply with MISRA · 2271cb05
      Jonathan Wright authored 
      

Initializes each element of the last_cpu_in_non_cpu_pd array in PSCI
stat implementation to -1, the reset value. This satisfies MISRA rule
9.3.

Previously, only the first element of the array was initialized to -1.

Change-Id: I666c71e6c073710c67c6d24c07a219b1feb5b773
Signed-off-by: default avatarJonathan Wright <jonathan.wright@arm.com>
      2271cb05
    • Joel Hutton's avatar
      Clean usage of void pointers to access symbols · 9f85f9e3
      Joel Hutton authored 
      

Void pointers have been used to access linker symbols, by declaring an
extern pointer, then taking the address of it. This limits symbols
values to aligned pointer values. To remove this restriction an
IMPORT_SYM macro has been introduced, which declares it as a char
pointer and casts it to the required type.

Change-Id: I89877fc3b13ed311817bb8ba79d4872b89bfd3b0
Signed-off-by: default avatarJoel Hutton <Joel.Hutton@Arm.com>
      9f85f9e3
  13. 26 Mar, 2018 1 commit
  15. 21 Mar, 2018 1 commit
    • Antonio Nino Diaz's avatar
      Rename 'smcc' to 'smccc' · 085e80ec
      Antonio Nino Diaz authored 
      

When the source code says 'SMCC' it is talking about the SMC Calling
Convention. The correct acronym is SMCCC. This affects a few definitions
and file names.

Some files have been renamed (smcc.h, smcc_helpers.h and smcc_macros.S)
but the old files have been kept for compatibility, they include the
new ones with an ERROR_DEPRECATED guard.

Change-Id: I78f94052a502436fdd97ca32c0fe86bd58173f2f
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
      085e80ec
  17. 15 Mar, 2018 1 commit
  19. 14 Mar, 2018 2 commits
  21. 28 Feb, 2018 3 commits
  23. 27 Feb, 2018 9 commits
  25. 22 Feb, 2018 1 commit
  27. 08 Feb, 2018 1 commit
  29. 07 Feb, 2018 1 commit
  31. 05 Feb, 2018 1 commit
    • Etienne Carriere's avatar
      aarch32: optee: define the OP-TEE secure payload · 10c66958
      Etienne Carriere authored 
      

AArch32 only platforms can boot the OP-TEE secure firmware as
a BL32 secure payload. Such configuration can be defined through
AARCH32_SP=optee.

The source files can rely on AARCH32_SP_OPTEE to condition
OP-TEE boot specific instruction sequences.

OP-TEE does not expect ARM Trusted Firmware formatted structure
as boot argument. Load sequence is expected to have already loaded
to OP-TEE boot arguments into the bl32 entrypoint info structure.

Last, AArch32 platform can only boot AArch32 OP-TEE images.

Change-Id: Ic28eec5004315fc9111051add6bb1a1d607fc815
Signed-off-by: default avatarEtienne Carriere <etienne.carriere@linaro.org>
      10c66958
  33. 01 Feb, 2018 3 commits
    • Masahiro Yamada's avatar
      zlib: add gunzip() support · c43d6851
      Masahiro Yamada authored 
      

This commit adds some more files to use zlib from TF.

To use zlib, ->zalloc and ->zfree hooks are needed.  The implementation
depends on the system.  For user-space, the libc provides malloc() and
friends.  Unfortunately, ARM Trusted Firmware does not provide malloc()
or any concept of dynamic memory allocation.

I implemented very simple calloc() and free() for this.  Stupidly,
zfree() never frees memory, but it works enough for this.

The purpose of using zlib is to implement gunzip() - this function
takes compressed data from in_buf, then dumps the decompressed data
to oub_buf.  The work_buf is used for memory allocation during the
decompress.  Upon exit, it updates in_buf and out_buf.  If successful,
in_buf points to the end of input data, out_buf to the end of the
decompressed data.

To use this feature, you need to do:

 - include lib/zlib/zlib.mk from your platform.mk

 - add $(ZLIB_SOURCES) to your BL*_SOURCES
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      c43d6851
    • Masahiro Yamada's avatar
      zlib: import zlib files from zlib 1.2.11 · 221b1638
      Masahiro Yamada authored 
      Import the following files from zlib 1.2.11:

   adler32.c
   crc32.c
   crc32.h
   inffast.c
   inffast.h
   inffixed.h
   inflate.c
   inflate.h
   inftrees.c
   inftrees.h
   zconf.h
   zlib.h
   zutil.c
   zutil.h

The original tarball is available from http://zlib.net/

The zlib is free software, distributed under the zlib license.  The
license text is included in the "zlib.h" file.  It should be compatible
with BSD-3-Clause.

The zlib license is included in the SPDX license list available at
https://spdx.org/licenses/

, but I did not add the SPDX license tag to
the imported files above, to keep them as they are in the upstream
project.  This seems the general policy for ARM Trusted Firmware, as
SPDX License Identifier was not added to files imported from FreeBSD.
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      221b1638
    • Masahiro Yamada's avatar
      misc_helpers: fix zero_normalmem() for BL2_AT_EL3 · 79c7e728
      Masahiro Yamada authored 
      

The assertion in zero_normalmem() fails for BL2_AT_EL3.  This mode is
executed in EL3, so it should check sctlr_el3 instead of sctlr_el1.
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
      79c7e728
  35. 31 Jan, 2018 2 commits
  37. 29 Jan, 2018 3 commits
  39. 19 Jan, 2018 2 commits
    • Julius Werner's avatar
      coreboot: Add support for CBMEM console · 1c5f5031
      Julius Werner authored 
      

coreboot supports an in-memory console to store firmware logs even when
no serial console is available. It is widely supported by
coreboot-compatible bootloaders (including SeaBIOS and GRUB) and can be
read by the Linux kernel.

This patch allows BL31 to add its own log messages to this console. The
driver will be registered automatically if coreboot support is compiled
in and detects the presence of a console buffer in the coreboot tables.

Change-Id: I31254dfa0c2fdeb7454634134b5707b4b4154907
Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      1c5f5031
    • Julius Werner's avatar
      Add platform-independent coreboot support library · 3429c77a
      Julius Werner authored 
      

This patch adds the foundation for a platform-independent coreboot
support library that can be shared by all platforms that boot BL31 from
coreboot (acting as BL2). It adds code to parse the "coreboot table", a
data structure that coreboot uses to communicate different kinds of
information to later-stage firmware and certain OS drivers.

As a first small use case for this information, allow platforms to
access the serial console configuration used by coreboot, removing the
need to hardcode base address and divisors and allowing Trusted Firmware
to benefit from coreboot's user configuration (e.g. which UART to pick
and which baud rate to use).

Change-Id: I2bfb39cd2609ce6640b844ab68df6c9ae3f28e9e
Signed-off-by: default avatarJulius Werner <jwerner@chromium.org>
      3429c77a