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The extra level of nesting is not necessary, drop it.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I6d268eae8df5794511d5211e5a59a36291adab3e

Use common qos_regs.h instead of a local copy in the M3N QoS init.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9670c9cdb320d6724175c22210d048af54490b47

Fix checkpatch issues, clean up macro indentation. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ifd397962c40d174c3af31cb440241cc8bd9335d3

The DBSC_SCFCTST2 is always written with the same value, no matter
what the MD pin value is, drop the entire check and just write the
register with the one and only possible value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Idf26cf064e99e95f0140dd747183efe6a6d7f0bf

Drop useless comments in dbsc_setting(). No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I4460c55bf58f33ca72c9bbad99a28b5e4ef7421e

The extra level of nesting is not necessary, drop it.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I086ab1f457866f0e2c3ccd67609c0be35631f893

Convert the mstat table from a complex structure to simple sequence
of uint64_t values, since the structure described just that and the
loop can operate over incrementing sequence of addresses just fine.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I41728b30087996edc9799f320bf6a3b4465538bd

Pull out the mstat fix array into separate file, to align the structure
of the driver with the other SoCs. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I21c18e80ab9225837e5553dadcf196605e878143

Use common qos_regs.h instead of a local copy in the M3W QoS init.
Fill missing registers into qos_regs.h . No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I91175c86cdb94b9271c880df2cb65949f15f1bad

Fix checkpatch issues, clean up macro indentation. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I605109b5e41219473a4cbc4a1929b84377ba0b67

The DBSC_SCFCTST2 is always written with the same value, no matter
what the MD pin value is, drop the entire check and just write the
register with the one and only possible value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I4d8926eb3c44c61ec777c05c581ce8247f13daa6

Drop useless comments in dbsc_setting(). No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I9e3d025567ff4e10e2b4448e8a518b4eee13f6c5

The extra level of nesting is not necessary, drop it.
No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I7b55a6fa53145ff0427e05656234917f486031df

Convert the mstat table from a complex structure to simple sequence
of uint64_t values, since the structure described just that and the
loop can operate over incrementing sequence of addresses just fine.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I379a1a5dfe2095d9477b364393ab120c4d8e1ba4

Pull out the mstat fix array into separate file, to align the structure
of the driver with the other SoCs. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ia92abe11c425220a065d707c350644c955efef92

Use common qos_regs.h instead of a local copy in the H3 QoS init.
Fill missing registers into qos_regs.h . No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I0b5ceab71be07e270885bdff403e5292e3373787

Convert the R-Car Gen3 platform and both SCIF and Log drivers
to multi-console API.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: I18556973937d150b60453f9150d54ee612571e35

BL2U should not build when RESET_TO_SP_MIN flag is set, like BL1 and
BL2.

Change-Id: Iac516121f98611ca1f58d2b5efdec6525b06ce4e
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Also sort alphabetically the links at the bottom, a couple of them were
not sorted.

Change-Id: I49a1dbe9e56a36c5fdbace8e4c8b9a5270bc2984
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

* changes:
  ti: k3: common: Remove coherency workaround for AM65x
  ti: k3: common: Use coherent memory for shared data

Provide the friendly marketing names, not just the platform name.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: Id4427abb73d0c1be4ac1709b2a8e87beffc20dd5

When acquiring or releasing the power domain locks for a given CPU the
parent nodes are looked up by walking the up the PD tree list on both the
acquire and release path, only one set of lookups is needed. Fetch the
parent nodes first and pass this list into both the acquire and release
functions to avoid the double lookup.

This also allows us to not have to do this lookup after coherency has
been exited during the core power down sequence. The shared struct
psci_cpu_pd_nodes is not placed in coherent memory like is done
for psci_non_cpu_pd_nodes and doing so would negatively affect
performance. With this patch we remove the need to have it in coherent
memory by moving the access out of psci_release_pwr_domain_locks().
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I7b9cfa9d31148dea0f5e21091c8b45ef7fe4c4ab

Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in
older revisions of the Neoverse N1 processor core.
The workaround is to set a bit in the implementation defined CPUACTLR2_EL1
system register, which will disable the load-bypass-store feature.

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html



Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the last accessed areas all being marked as non-cached by
USE_COHERENT_MEM we can rely on that to workaround our interconnect
issues. Remove the old workaround.

Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7
Signed-off-by: Andrew F. Davis <afd@ti.com>

HW_ASSISTED_COHERENCY implies something stronger than just hardware
coherent interconnect, specifically a DynamIQ capable ARM core.

For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early
and then let the caches get shut off on powerdown, to prevent data
corruption we also need to USE_COHERENT_MEM so that any accesses to
shared memory after this point is only to memory that is set as
non-cached for all cores.

Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949
Signed-off-by: Andrew F. Davis <afd@ti.com>

add mcsi driver to support cache coherence.

Change-Id: I94f5922783e5dbc6b7e92aa06464bc1f0177f00a
Signed-off-by: kenny liang <kenny.liang@mediatek.com>

Add Mediatek GIC driver to support interrupt functions.
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
Change-Id: I967a18f2e45b7bbc88c506dd4f1f40a745227ad9

Change-Id: I0d9dbef7041fcf950bcafcdbbc17c72b4dea9e40
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

During the secondary cores' cold boot path, the cores initialise the GIC
CPU interface. However this is a redundant action since 1) the cores are
powered down immediately after that, 2) the GIC CPU interface is
initialised from scratch when the secondary cores are powered up again
later.

Moreover, this part of code was introducing a bug. In a GICv3 system,
the GIC's CPU interface system registers must not be written without the
core being marked as "awake" in the redistributor. However, this
sequence was performing such accesses and this would cause those cores
to hang. The hang was caused by the DSB instruction that would never
complete because of the GIC not recognising those writes.

For the two aforementioned reasons, the entire part of the GIC CPU
interface initialisation is removed.

Change-Id: I6c33a1edda69dd5b6add16a27390a70731b5532a
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

According to Arm GIC spec(IHI0069E, section 4.6.1),
when GICD_CTLR.DS == 0, Secure Group 1 interrupts
are treated as Group 0 by a CPU interface if:
- The PE does not implement EL3.
- ICC_SRE_EL1(S).SRE == 0

When a cpu enter suspend or deep idle, it might be
powered off. When the cpu resume, according to
the GIC spec(IHI0069E, section 9.2.15, 9.2.16 and
9.2.22) the ICC_SRE_EL1.SRE reset value is 0 (if
write is allowed) and G0/G1S/G1NS interrupt of the
GIC cpu interface are all disabled.

If a G1S SPI interrupt occurred and the target cpu
of the SPI is assigned to a specific cpu which is
in suspend and is powered off, when the cpu resume
and start to initial the GIC cpu interface, the
initial sequence might affect the interrupt group
type of the pending interrupt on the cpu interface.

Current initial sequence on the cpu interface is:
1. Enable G0 interrupt
2. Enable G1S interrupt
3. Enable ICC_SRE_EL1(S).SRE

It is possible to treat the pending G1S interrupt
as G0 interrupt on the cpu interface if the G1S
SPI interrupt occurred between step2 and step3.

To prevent the above situation happend, the initial
sequence should be changed as follows:
1. Enable ICC_SRE_EL1(S).SRE
2. Enable G0 interrupt
3. Enable G1S interrupt

Change-Id: Ie34f6e0b32eb9a1677ff72571fd4bfdb5cae25b0
Signed-off-by: James Kung <kong1191@gmail.com>