- 16 Jan, 2019 18 commits
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] convert object type to match the type of function parameters [Rule 10.3] Force operands of an operator to the same type category [Rule 10.4] Fix implicit widening of composite assignment [Rule 10.6] Change-Id: I5840a07f37beefc3326ac56d0b4a4701602bd8a8 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
This patch removes unwanted error prints from the MCE command handler, to reduce the code complexity for this function. Tested with 'pmccabe' Change-Id: I375d289db1df9e119eeb1830210974457c8905a4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
This patch removes support for the SC8 power state as the feature is no longer required for Tegra186 projects. Change-Id: I622a5ddcffe025b9b798801d09bbb856853befd7 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses [Rule 20.7] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix implicit widening of composite assignment [Rule 10.6] Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] Force operands of an operator to the same type category [Rule 10.4] Voided non c-library functions whose return types are not used [Rule 17.7] Change-Id: I758e7ef6d45dd2edf4cd5580e2af15219246e75c Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Varun Wadekar authored
* EKS blob size was not passed by as a boot parameter earlier. Its being passed now * If EKS value sent by bootloader is non-zero update the boot parameter from default value to the argument passed by bootloader Change-Id: I65a3091bd2c1c908cc9e81c0aab6489cab02c098 Signed-off-by: Akshay Sharan <asharan@nvidia.com>
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Sam Payne authored
DRBG must be initialized to guarantee SRK has a random value during suspend. This patch add a sequence to generate an SRK on boot and during resume for SE1 and SE2. This SRK value is not saved to PMC scratch, and should be overwitten during atomic suspend. Change-Id: Id5e2dc74a1b462dd6addaec1709fec46083a6e1c Signed-off-by: Sam Payne <spayne@nvidia.com>
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Varun Wadekar authored
This patch adds the driver to communicate with the BPMP processor for power management use cases. BPMP controls the entry into cluster and system power states. The Tegra210 platform port queries the BPMP to calculate the target state for the cluster. In case BPMP does not allow CCx entry, the core enters a power down state. Change-Id: I9c40aef561607a0b02c49b7f8118570eb9105cc9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
This patch fixes MISRA defects for the MCE driver. * Using logical NOT for bool type function * Using MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS replace MPIDR_CLUSTER_MASK Change-Id: I97e96f172a3c1158646a15a184c273c53a103d63 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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Anthony Zhou authored
This patch uses int32_t to replace ints, to fix Rule 4.6 of the MISRA standard. Change-Id: I20ac6185929eced684b43da3ef1f8cd5fbddc83d Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
This patch adds (void) for unused function parameters to fix Rule 2.7 of the MISRA standard. Change-Id: Ibc3f10b3bfe73363383b4c28413ab8d99fbc8c89 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Marvin Hsu authored
This patch adds the implementation of the SE atomic context save sequence. The atomic context-save consistently saves to the TZRAM carveout; thus there is no need to declare context save buffer or map MMU region in TZRAM for context save. The atomic context-save routine is responsible to validate the context-save progress counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error status to ensure the context save procedure complete successfully. Change-Id: Ic80843902af70e76415530266cb158f668976c42 Signed-off-by: Marvin Hsu <marvinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
Main fixes: * Expressions resulting from the expansion of macro parameters shall be enclosed in parentheses [Rule 20.7] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix implicit widening of composite assignment [Rule 10.6] Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Harvey Hsieh authored
This patch adds capability to read the boot flag to enable L2 ECC and Parity Protection bit for the Cortex-A57 CPUs. The previous bootloader sets this flag value for the platform. * with some coverity fix: MISRA C-2012 Directive 4.6 MISRA C-2012 Rule 2.5 MISRA C-2012 Rule 10.3 MISRA C-2012 Rule 10.4 Change-Id: Id7303bbbdc290b52919356c31625847b8904b073 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Harvey Hsieh authored
This patch sets up the clock for the UART console, for real Silicon and FPGA platforms. FPGA platforms run the UART clock source at 13MHz, whereas the clock cource runs at 408MHz for real silicon. Change-Id: Ibfd99df032ec473f29e636e597cfc95a0f580598 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Marvin Hsu authored
This patch adds helper functions to find out the chip ID of the Tegra SoC. Change-Id: Ia3901dc7cdf77d8c23884d1ed38a80dba6a8afde Signed-off-by: Marvin Hsu <marvinh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Varun Wadekar authored
The platform code generates the power domain tree. The handler to retrieve the tree should also reside in the platform code. This patch moves the plat_get_power_domain_tree_desc() to the individual platforms. Change-Id: Iaafc83ed381d83129501111ef655e3c58a8a553f Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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Anthony Zhou authored
This patch adds support for simulation platforms as well as fixes issues flagged by the MISRA scans. Main MISRA fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Fix return type doesn't match the function type [Rule 10.3] * Use single return point instead of multiple [Rule 15.5] * Change return type for the tegra_platform_is_x handlers to bool Change-Id: I871b7c37b22942f6c0c2049c14cc626d4a24d81c Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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- 15 Jan, 2019 7 commits
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Ard Biesheuvel authored
Enable the deprecated SPM framework for the SynQuacer platform. It involves creating a memory layout in secure DRAM, and wiring up the SPM infrastructure so that the secure partition payload that is loaded into this region by the SCP firmware is dispatched appropriately. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Ard Biesheuvel authored
The logic that initializes the BL32 entry point data structure should only be executed if we are in fact loading OP-TEE, and not if BL32_BASE is set for other reasons (i.e., when enabling SPM) Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Paul Beesley authored
Corrects typos in core code, documentation files, drivers, Arm platforms and services. None of the corrections affect code; changes are limited to comments and other documentation. Change-Id: I5c1027b06ef149864f315ccc0ea473e2a16bfd1d Signed-off-by: Paul Beesley <paul.beesley@arm.com>
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Antonio Nino Diaz authored
From now on, platform_def.h must include any header with definitions that are platform-specific (like arm_def.h) and the included headers mustn't include back platform_def.h, and shouldn't be used by other files. Only platform_def.h should be included in other files. This will ensure that all needed definitions are present, rather than needing to include all the headers in all the definitions' headers just in case. This also prevents problems like cyclic dependencies. Change-Id: I9d3cf4d1de4b956fa035c79545222697acdaf5ca Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Antonio Nino Diaz authored
The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for platforms that may need to access them. Change-Id: Ifd1880f855ddafcb3bfcaf1ed4a4e0f121eda174 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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Anson Huang authored
With DEBUG_CONSOLE enabled, build will fail for imx8mq platform: ./build/imx8mq/release/bl31/imx8mq_bl31_setup.o: In function `bl31_early_platform_setup2': imx8mq_bl31_setup.c:(.text.bl31_early_platform_setup2+0x40): undefined reference to `console_uart_register' Makefile:741: recipe for target 'build/imx8mq/release/bl31/bl31.elf' failed make: *** [build/imx8mq/release/bl31/bl31.elf] Error 1 Besides, the .console_flush callback needs to be added to avoid panic when debug mode is enabled, since the console_flush() will call it without checking whether the function callback is valid. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Anson Huang authored
Current lpuart driver does NOT implement .console_flush callback, if debug console is enabled, the console_flush() will call the undefined .console_flush callback(NULL) for lpuart and leak to panic, this patch adds .console_flush callback to make lpuart work for debug mode. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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- 10 Jan, 2019 2 commits
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Joel Hutton authored
Change-Id: I7194a9a5f0e41308eb3242d20c0d3434f72da591 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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Joel Hutton authored
It is cleaner to use the same number of tables regardless of whether OP-TEE is used or not. This doesn't result in a significant memory usage increase. Change-Id: I38bcaa3f2f197c0a352153117592749f189a265c Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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- 09 Jan, 2019 9 commits
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Jolly Shah authored
pm_service ipi functions can be used by other xilinx platforms. So move it to common directory. Also change node_id member type in pm_proc structure so it can be used for versal where device IDs are used instead of node IDs. To accommodate this change header files are re-organized. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Jolly Shah authored
ZynqMP pm_service ipi file uses platform specific macros names. pm_service ipi functions can be used by other Xilinx platforms also. Make rename macros to use generic names so that it can be used by common file. pm_service ipi functions will be moved to common file in next patch. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Jolly Shah authored
Use generic name for pm_api structure member, so that pm_api structure can be used other Xilinx platforms. Structure definition will be moved to common file in upcoming patch. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Jolly Shah authored
ipi_mb functions can be used for other Xilinx platform. Move it to common file from platform specific files. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Jolly Shah authored
ipi_mb function uses platform specific ipi configuration table. These ipi_mb functions can be used for other Xilinx platform. So, instead of using direct data structure, initialize IPI configuration data by passing platform specific ipi table. Macros are updated accordingly for this ipi table change. This change is done so that ipi_mb functions can be moved to common file without major changes. All common functions now would be moved to common file in next patch. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Jolly Shah authored
Move ipi configuration structure definition to common header file and rename it to common name, so it can be used for Xilinx specific other platforms in upcoming changes. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Jolly Shah authored
Move zynqmp_ipi.h to platform specific include directory. Rename it to plat_ipi.h instead of platform name. So, it can be used to common source files which needs platform specific data. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Jolly Shah authored
Move zynqmp_def.h to platform specific include directory. Also, update source file to include header file from updated path of zynqmp_def.h Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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Jolly Shah authored
Move zynqmp_private.h to platform specific include directory. Also, rename it to plat_private.h instead of having platform name. So, it can be used to common source files which needs platform specific data. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Jolly Shah <jollys@xilinx.com>
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- 08 Jan, 2019 4 commits
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Joel Hutton authored
A previous commit 89f2e589 ("plat/arm: remove weak implemention of 'plat_arm_psci_override_pm_ops' function") introduced a problem with the CSS_USE_SCMI_SDS_DRIVER configuration. In juno_pm.c the css_scmi_override_pm_ops function was used regardless of whether the flag was set. This patch ifdefs the function to restore the original behaviour. Change-Id: I508025ba70cf3a9250cc6270c1df209179c37ae7 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
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Ard Biesheuvel authored
Update some asserts that refer to #defines that only occur in ARM platforms, preventing this code to be used on other platforms. Instead, use a platform agnostic name, and update all the existing users. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Marek Vasut authored
Update the reported Renesas version to 2.0.0, since the DDR/QoS/PFC table versions match the ones from that release. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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Marek Vasut authored
Replace the ad-hoc implementation of delay in PWRC driver with common R-Car delay code. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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