- 25 Aug, 2016 1 commit
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dp-arm authored
It should be 'fiptool' instead of 'fiptfool'. Change-Id: I84ce1b6aaae5b8b33e5781bfe4f9e9cf462edb03
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- 17 Aug, 2016 4 commits
- 16 Aug, 2016 1 commit
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Sandrine Bailleux authored
This patch updates the User Guide to move up from version 7.2 to 7.6 of the Base FVP. Change-Id: I792b2250deb4836266e14b40992ae59a5ab5f729
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- 15 Aug, 2016 1 commit
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dp-arm authored
The output is shown only when built with V=1. Change-Id: I17fef10df6f127f07956a78b478ff3cadba4bd61
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- 12 Aug, 2016 2 commits
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danh-arm authored
Support pwm for rk3399
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Haojian Zhuang authored
Support CMD23. When CMD23 is used, CMD12 could be avoided. Two scenarios: 1. CMD17 for single block, CMD18 + CMD12 for multiple blocks. 2. CMD23 + CMD18 for both single block and multiple blocks. The emmc_init() should initialize whether CMD23 is supported or not. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 11 Aug, 2016 4 commits
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Sudeep Holla authored
As per the GICv3 specification, to power down a processor using GICv3 and allow automatic power-on if an interrupt must be sent to a processor, software must set Enable to zero for all interrupt groups(by writing to GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate. Also, NonSecure EL1 software may not be aware of the CPU power state details and fail to choose right states that require quiescing the CPU interface. So it's preferred that the PSCI implementation handles it as it is fully aware of the CPU power states. This patch adds disabling of Group1 NonSecure interrupts during processor power down along with Group0 and Group1 Secure interrupts so that all the interrupt groups are handled at once as per specification. Change-Id: Ib564d773c9c4c41f2ca9471451c030e3de75e641
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Caesar Wang authored
The pmusgrf reset-hold bits needs to be released, since the pmusgrf reset-hold bits needs to be held. Change-Id: Ia1eccc8fba18294f26b4cc07d47bc5e513dd9a1f
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Caesar Wang authored
Sometimes this will cause the long delay for suspend/resume. Since the 24M OCS will be turned off in power mode. Also, remove the ERROR_DEPRECATED config define. Change-Id: I78f21c35912c2250972e551695cdacc7bc4c020a
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Caesar Wang authored
This patch updates some things for rk3399, as following: 1) Add the new file to handle the pwm. (e.g. the pwm regulator) Make sure that good deal with the pwm related things. Also, remove some pwm setting for pmu.c. 2) Set the plls slow mode and bypass in suspend, and restore them. Change-Id: I112806700bf433c87763aac23d22fa7e6a7f5264
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- 09 Aug, 2016 2 commits
- 04 Aug, 2016 1 commit
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Haojian Zhuang authored
If buffer address parameter isn't aligned, it may cause DMA issue in block device driver, as eMMC. Now check the buffer address. If it's not aligned, use temporary buffer in io block driver instead. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
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- 29 Jul, 2016 1 commit
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dp-arm authored
fiptool provides a more consistent and intuitive interface compared to the fip_create program. It serves as a better base to build on more features in the future. fiptool supports various subcommands. Below are the currently supported subcommands: 1) info - List the images contained in a FIP file. 2) create - Create a new FIP file with the given images. 3) update - Update an existing FIP with the given images. 4) unpack - Extract a selected set or all the images from a FIP file. 5) remove - Remove images from a FIP file. This is a new command that was not present in fip_create. To create a new FIP file, replace "fip_create" with "fiptool create". To update a FIP file, replace "fip_create" with "fiptool update". To dump the contents of a FIP file, replace "fip_create --dump" with "fiptool info". A compatibility script that emulates the basic functionality of fip_create is provided. Existing scripts might or might not work with the compatibility script. Users are strongly encouraged to migrate to fiptool. Fixes ARM-Software/tf-issues#87 Fixes ARM-Software/tf-issues#108 Fixes ARM-Software/tf-issues#361 Change-Id: I7ee4da7ac60179cc83cf46af890fd8bc61a53330
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- 28 Jul, 2016 7 commits
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danh-arm authored
Documentation for SEPARATE_CODE_AND_RODATA build flag
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Sandrine Bailleux authored
This patch documents the effect, cost and benefits of the SEPARATE_CODE_AND_RODATA build flag. Change-Id: Ic8daf0563fa6335930ad6c70b9c35f678e84d39d
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danh-arm authored
rockchip: fixes typo and some bugs for suspend/resume tests
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danh-arm authored
Improve debug assertion for runtime svc number
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danh-arm authored
GICv3: Fix the GICD_IROUTER offset
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danh-arm authored
ARM platforms: Define common image sizes
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Caesar Wang authored
1. Remove the AP_PWROFF in ATF, should configure it in kernel. 2. Save and restore the PWMs pin/regs for suspend/resume. 3. The pmusgrf reset-hold bits needs to be released. since the pmusgrf reset-hold bits needs to be held. 4. Configure the PMU power up/down cycles about delay 3ms. 5. With the MMIO register block as one big mapping. 6. Fix the build error with psci_entrypoint since PSCI lib updated. Fixes the commit 9ec78bdf ("rockchip: support the suspend/resume for rk3399"). Change-Id: I112806700bf433c87763aac23d22fa7e6a7f5264
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- 27 Jul, 2016 1 commit
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Soby Mathew authored
This patch fixes the offset of GICD_IROUTER register defined in gicv3.h. Although the GICv3 documention mentions that the offset for this register is 0x6100-0x7FD8, the offset calculation for an interrupt id `n` is : 0x6000 + 8n, where n >= 32 This requires the offset for GICD_IROUTER to be defined as 0x6000. Fixes ARM-software/tf-issues#410 Change-Id: If9e91e30d946afe7f1f60fea4f065c7567093fa8
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- 26 Jul, 2016 3 commits
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Soby Mathew authored
This patch improves the debug assertion for runtime svc number - Remove useless comparison ensuring that the number of descriptors is a positive number. The variable is an unsigned integer so can't be negative. - Check that the end address of the descriptors is sane relative to the start address. Change-Id: Iea7be6b34e33b8b1cbd394eb923cc834ea964831
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danh-arm authored
Fix use of stale power states in PSCI standby finisher
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danh-arm authored
Minor improvements to harden TF code
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- 25 Jul, 2016 7 commits
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Achin Gupta authored
A PSCI CPU_SUSPEND request to place a CPU in retention states at power levels higher than the CPU power level is subject to the same state coordination as a power down state. A CPU could implement multiple retention states at a particular power level. When exiting WFI, the non-CPU power levels may be in a different retention state to what was initially requested, therefore each CPU should refresh its view of the states of all power levels. Previously, a CPU re-used the state of the power levels when it entered the retention state. This patch fixes this issue by ensuring that a CPU upon exit from retention reads the state of each power level afresh. Change-Id: I93b5f5065c63400c6fd2598dbaafac385748f989
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Sandrine Bailleux authored
This patch adds some runtime checks to prevent some potential pointer overflow issues in the is_mem_free() function. The overflow could happen in the case where the end addresses, computed as the sum of a base address and a size, results in a value large enough to wrap around. This, in turn, could lead to unpredictable behaviour. If such an overflow is detected, the is_mem_free() function will now declare the memory region as not free. The overflow is detected using a new macro, called check_uptr_overflow(). This patch also modifies all other places in the 'bl_common.c' file where an end address was computed as the sum of a base address and a size and instead keeps the two values separate. This avoids the need to handle pointer overflows everywhere. The code doesn't actually need to compute any end address before the is_mem_free() function is called other than to print information message to the serial output. This patch also introduces 2 slight changes to the reserve_mem() function: - It fixes the end addresses passed to choose_mem_pos(). It was incorrectly passing (base + size) instead of (base + size - 1). - When the requested allocation size is 0, the function now exits straight away and says so using a warning message. Previously, it used to actually reserve some memory. A zero-byte allocation was not considered as a special case so the function was using the same top/bottom allocation mechanism as for any other allocation. As a result, the smallest area of memory starting from the requested base address within the free region was reserved. Change-Id: I0e695f961e24e56ffe000718014e0496dc6e1ec6
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Sandrine Bailleux authored
- Added some debug assertions checking that the runtime services indexes computed by get_unique_oen() are sane. - Do not print the name of the service when its descriptor is invalid. If the descriptor is corrupted then its name field could be corrupted as well and we would end up reading an arbitrary amount of invalid memory. Change-Id: I16f61065277d01fe1555d5a9cf743f7b52ccaa60
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Sandrine Bailleux authored
Light refactoring of the code in runtime_svc.c file. - Declare validate_rt_svc_desc()'s argument as const. - Remove 'goto' path in runtime_svc_init(). It was used in one place only. - Improve code readability by declaring a local variable holding the service pointer. Change-Id: I3b15c5adb9f37b786b5b993a9be70ea9dd017a83
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Sandrine Bailleux authored
This patch adds a runtime check that psci_find_target_suspend_lvl() returns a valid value back to psci_cpu_suspend() and psci_get_stat(). If it is invalid, BL31 will now panic. Note that on the PSCI CPU suspend path there is already a debug assertion checking the validity of the target composite power state, which effectively also checks the validity of the target suspend level. Therefore, the error condition would already be caught in debug builds, but in a release build this assertion would be compiled out. On the PSCI stat path, there is currently no debug assertion checking the validity of the power state before using it as an index into the power domain state array. Although BL31 platforms ports are responsible for validating the power state parameter, the security impact (i.e. an out-of-bounds array access) of a potential platform port bug in this code would be quite high, given that this parameter comes from an untrusted source. The cost of checking this in runtime generic code is low. Change-Id: Icea85b8020e39928ac03ec0cd49805b5857b3906
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danh-arm authored
Introduce PSCI library
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Antonio Nino Diaz authored
Compile option `ARM_BOARD_OPTIMISE_MMAP` has been renamed to `ARM_BOARD_OPTIMISE_MEM` because it now applies not only to defines related to the translation tables but to the image size as well. The defines `PLAT_ARM_MAX_BL1_RW_SIZE`, `PLAT_ARM_MAX_BL2_SIZE` and `PLAT_ARM_MAX_BL31_SIZE` have been moved to the file board_arm_def.h. This way, ARM platforms no longer have to set their own values if `ARM_BOARD_OPTIMISE_MEM=0` and they can specify optimized values otherwise. The common sizes have been set to the highest values used for any of the current build configurations. This is needed because in some build configurations some images are running out of space. This way there is a common set of values known to work for all of them and it can be optimized for each particular platform if needed. The space reserved for BL2 when `TRUSTED_BOARD_BOOT=0` has been increased. This is needed because when memory optimisations are disabled the values for Juno of `PLAT_ARM_MMAP_ENTRIES` and `MAX_XLAT_TABLES` are higher. If in this situation the code is compiled in debug mode and with "-O0", the code won't fit. Change-Id: I70a3d8d3a0b0cad1d6b602c01a7ea334776e718e
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- 19 Jul, 2016 5 commits
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Soby Mathew authored
This patch moves assembler macros which are not architecture specific to a new file `asm_macros_common.S` and moves the `el3_common_macros.S` into `aarch64` specific folder. Change-Id: I444a1ee3346597bf26a8b827480cd9640b38c826
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Soby Mathew authored
Previously the definition of `plat_get_syscnt_freq2()` in `arm_common.c` was conditionally defined based on the ERROR_DEPRECATED flag. This patch makes this function available irrespective of the flag and removes the deprecated `plat_get_syscnt_freq()` definition. Change-Id: I250ca787ca1b5e867096c6ba8f2bb444db44c97b
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Soby Mathew authored
The PRELOADED_BL33_BASE build option allows to preload a BL33 and bypass its loading by BL2. In ARM standard platforms, the conditional behaviour of PRELOADED_BL33_BASE is moved within the implementation of `plat_get_ns_image_entrypoint()` so that all callers may benefit from this feature. Change-Id: Iea060e204ec72f8081087837854535c4e320da4e
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Soby Mathew authored
This patch moves the `arm_common.c` file from `plat/arm/common/aarch64/` to the parent directory since the functions implemented in the file are not AArch64 specific. The platform makefiles are also modified for this change. Change-Id: I776d2e4958f59041476cf2f53a9adb5b2d304ee0
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Soby Mathew authored
The `plat_psci_common.c` was moved to the new location `plat/common` and a stub file was retained at previous location for compatibility. This patch modifies the platform makefiles to include the file from the new location. Change-Id: Iabddeeb824e9a5d72d176d7c644735966c8c0699
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