- 19 Aug, 2019 1 commit
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Hadi Asyrafi authored
Driver will calculate DDR size instead of using hardcoded value Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I642cf2180929965ef12bd5ae4393b2f3d0dcddde
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- 15 Aug, 2019 5 commits
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Paul Beesley authored
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Paul Beesley authored
* changes: rockchip: rk3399: store actual debug uart information on suspend rockchip: move dt-coreboot uart distinction into param handling code rockchip: make uart baudrate configurable rockchip: px30: add uart5 as option for serial output
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Paul Beesley authored
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Alexei Fedorov authored
This patch modifies crash reporting for AArch64 to provide aligned output of register dump and GIC registers. Change-Id: I8743bf1d2d6d56086e735df43785ef28051c5fc3 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Hadi Asyrafi authored
Increase calibration delay, fix ddrio control config & nonsecure region limit Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ibca3c247a3ad5104176ca9057d29755599f13c9b
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- 14 Aug, 2019 2 commits
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Paul Beesley authored
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Hadi Asyrafi authored
Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
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- 13 Aug, 2019 1 commit
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Paul Beesley authored
* changes: Fix Coverity #261967, Infinite loop Fix Coverity #343017, Missing unlock Fix Coverity #343008, Side affect in assertion Fix Coverity #342970, Uninitialized scalar variable
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- 12 Aug, 2019 1 commit
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Alexei Fedorov authored
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- 09 Aug, 2019 2 commits
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Heiko Stuebner authored
The rk3399 suspend code saves and restores the debug uart settings, but right now always does this for the default uart. Right now this works only by chance for the majority of rk3399 boards, which do not deviate from that default. But both Coreboot as well as U-Boot-based platforms can actually use different uarts for their output, which can be configured from either devicetree or Coreboot-variables. To fix this, just use the stored uart-base information instead of the default constant. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I1ea059d59a1126f6f8702315df7e620e632b686e
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Heiko Stuebner authored
Rockchip platforms can be booted from either u-boot or coreboot. So far the Coreboot-console was initizalized from a coreboot data struct in the early_param2 callbacks and dt-based consoles with data from the rockchip_get_uart_* functions. But later code may also need this console information for example for special suspend handling. To make this easy follow a suggestion from Julius Werner and move the coreboot<->dt distinction into the rockchip_get_uart_* functions, thus making correct data about the used uart available to all Rockchip platform code at all times. This includes a new rockchip_get_uart_clock as well, because while the dt-platforms right now always just default the rate defined in a constant Coreboot provides its own field for the clock rate and we don't want to loose that information for the console init. Similarly the rk_uart_* variables should move into the non-Coreboot code, to prevent them from being marked as unused, which also requires the rk_get_uart_* functions to move below the actual dt-parsing. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I278d595d2aa6c6864187fc8979a9fbff9814feac
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- 07 Aug, 2019 2 commits
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Sandrine Bailleux authored
* changes: intel: Platform common code refactor intel: Platform common code refactor
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Hadi Asyrafi authored
Pull out common code from aarch64 and include Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645f
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- 06 Aug, 2019 6 commits
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Sandrine Bailleux authored
* changes: plat/qemu: add gicv3 support for qemu plat/qemu: move gicv2 codes to separate file
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Justin Chadwell authored
Coverity has identified that the __aeabi_imod function will loop forever if the denominator is not a power of 2, which is probably not the desired behaviour. The functions in the rest of the file are compiler implementations of division if ARMv7 does not implement division which is permitted by the spec. However, while most of the functions in the file are documented and referenced in other places online, __aeabi_uimod and __aeabi_imod are not. For this reason, these functions have been removed from the code base, which also removes the Coverity error. Change-Id: I20066d72365329a8b03a5536d865c4acaa2139ae Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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Justin Chadwell authored
All other returns from this function unlock the responses_lock, so we also should release the lock in this case. Change-Id: Ie2cfa8755723fed79e809f9480190d11f373a217 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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Justin Chadwell authored
This patch simply splits off the increment of next_xlat into a separate statement to ensure consistent behaviour if the assert was to ever be removed. Change-Id: I827f601ccea55f4da9442048419c9b8cc0c5d22e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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Justin Chadwell authored
This ensures that probe_data starts with a reasonable default, as opposed to whatever was left on the stack. Change-Id: I5550efea5e2bec7717f9fa063cb11e6a7005cce5 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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Sandrine Bailleux authored
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- 05 Aug, 2019 3 commits
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Heiko Stuebner authored
A previous patch already allowed to configure the uart output from the devicetree, but on Rockchip platforms we also have the issue of different vendors using different baudrates for their uarts. For example, rk3399 has a default baudrate of 115200 which is true for ChromeOS-devices and boards from Theobroma-Systems, while all the boards using the vendor boot chain actually use a baudrate of 1500000. Similarly the newly added px30 has a default of said 1500000 but some boards may want to use the more widely used 115200. The devicetree stdout-path node already contains the desired baudrate, so add simple code to parse it from there and override the default, which stays unchanged. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: I7412139c3df3073a1996eb508ec08642ec6af90d
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Sumit Garg authored
Enable dispatcher to save/restore unbanked timer registers. So that both secure (OP-TEE) and non-secure (Linux) worlds can have independent access control over timer registers. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I4d58d5ff8298587ed478c8433fcbc3aef538d668
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Heiko Stuebner authored
The px30 mini-evb can use either uart2 (muxed with the sd-card pins) or uart5 via its pin header for serial output. Uart5 is especially useful when needing to boot from the sd-card, where uart2 obviously is not useable. So add the uart5 constants and it as uart option for the serial-param handler. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: Ib88df7a55d761ee104d312c9953a13de3beba1c4
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- 02 Aug, 2019 7 commits
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Alexei Fedorov authored
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Alexei Fedorov authored
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Hadi Asyrafi authored
Previous config blocks ATF runtime service communications with SDM mailbox Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ia857facd0bd0790056df94ed1e016bcf619a161e
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Remi Pommarel authored
The CPU[1-3] are reset to initial/cold boot state (with their reset address set to 0x0). In this state the cpus are waiting for another one to set the reset address to bl31_warm_entrypoint and wake them up. The CPU0 needs a bit of a workaround as changing the reset address either through PSCI mailbox or the mmio mapped RVBAR (at 0xda834650) does not seem to have any effect. Thus the workaround consists in emulating the other CPUs' behavior with a WFE loop and manually jumping to bl31_warm_entrypoint when woken back up by another one. Change-Id: I11265620b5fd0619285e3993253a3f9a3ff6a7a4 Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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Remi Pommarel authored
Before CPU enters standby state (wfi), the AP needs to signal the SCP through PSCI mailbox. Also at boot time the AP has to wait for the SCP to be ready before sending the first scpi commands or it can crash. Change-Id: Iacc99f5bec745ad71922c5ea07ca5b87088133b6 Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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Alexei Fedorov authored
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Alexei Fedorov authored
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- 01 Aug, 2019 5 commits
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Julius Werner authored
NOTE: AARCH32/AARCH64 macros are now deprecated in favor of __aarch64__. All common C compilers pre-define the same macros to signal which architecture the code is being compiled for: __arm__ for AArch32 (or earlier versions) and __aarch64__ for AArch64. There's no need for TF-A to define its own custom macros for this. In order to unify code with the export headers (which use __aarch64__ to avoid another dependency), let's deprecate the AARCH32 and AARCH64 macros and switch the code base over to the pre-defined standard macro. (Since it is somewhat unintuitive that __arm__ only means AArch32, let's standardize on only using __aarch64__.) Change-Id: Ic77de4b052297d77f38fc95f95f65a8ee70cf200 Signed-off-by: Julius Werner <jwerner@chromium.org>
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Julius Werner authored
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
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Alexei Fedorov authored
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Louis Mayencourt authored
At the time of writting, GCC 8.3-2019.03 is the latest version available on developer.arm.com. Switch to bare-metal toolchain (arm-eabi-) for AArch32. This allows to have a finer control on the use of floating-point and SIMD instructions. Change-Id: I4438401405eae1e5f6d531b0162e8fa06f69135e Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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Hadi Asyrafi authored
Pull out common code from agilex and stratix10 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc
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- 31 Jul, 2019 5 commits
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Alexei Fedorov authored
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Alexei Fedorov authored
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Balint Dobszay authored
Change-Id: Ie0a94783d0c8e111ae19fd592304e6485f04ca29 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
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Alexei Fedorov authored
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Alexei Fedorov authored
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