- 01 Aug, 2019 1 commit
-
-
Hadi Asyrafi authored
Pull out common code from agilex and stratix10 Signed-off-by:Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc
-
- 17 Jul, 2019 1 commit
-
-
Hadi Asyrafi authored
Signed-off-by:
-
- 04 Feb, 2019 1 commit
-
-
Loh Tien Hock authored
This adds BL2 support for Intel Stratix 10 SoC FPGA. Functionality includes: - Release and setup peripherals from reset - Calibrate DDR - ECC DDR Scrubbing - Load FIP (bl31 and bl33) Signed-off-by:Loh Tien Hock <tien.hock.loh@intel.com>
-
