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  1. 25 Jul, 2017 2 commits
    • Sandrine Bailleux's avatar
      FVP: Do not map DEVICE2 memory range when TBB is disabled · 284c3d67
      Sandrine Bailleux authored 
      

The DEVICE2 memory range is needed to access the Root of Trust Public
Key registers. This is not needed when Trusted Board Boot is disabled
so it's safer to not map it in this case. This also saves one level-2
page table in each of BL1 and BL2 images.

Also add some comments.

Change-Id: I67456b44f3fd5e145f6510a8499b7fdf720a7273
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      284c3d67
    • Sandrine Bailleux's avatar
      xlat lib v2: Print some debug statistics · 0350bc6d
      Sandrine Bailleux authored 
      

This patch adds some debug prints to display some statistics about page
tables usage. They are printed only if the LOG_LEVEL is at least 50
(i.e. VERBOSE).

Sample output for BL1:

VERBOSE:    Translation tables state:
VERBOSE:      Max allowed PA:  0xffffffff
VERBOSE:      Max allowed VA:  0xffffffff
VERBOSE:      Max mapped PA:   0x7fffffff
VERBOSE:      Max mapped VA:   0x7fffffff
VERBOSE:      Initial lookup level: 1
VERBOSE:      Entries @initial lookup level: 4
VERBOSE:      Used 4 sub-tables out of 5 (spare: 1)

Change-Id: If38956902e9616cdcd6065ecd140fe21482597ea
Signed-off-by: default avatarSandrine Bailleux <sandrine.bailleux@arm.com>
      0350bc6d
  3. 20 Jul, 2017 1 commit
  5. 14 Jul, 2017 6 commits
    • davidcunado-arm's avatar
      Merge pull request #1005 from ldts/v1 · 4deb7bcc
      davidcunado-arm authored 
      Poplar: Initial commit for Poplar E-96Boards
      4deb7bcc
    • davidcunado-arm's avatar
      Merge pull request #1028 from vchong/bl32_optee_support_v2 · 8f83003b
      davidcunado-arm authored 
      hikey: Add BL32 (OP-TEE) support v2
      8f83003b
    • Jorge Ramirez-Ortiz's avatar
      Poplar: Initial commit for Poplar E-96Boards · e35d0edb
      Jorge Ramirez-Ortiz authored 
      The board features the Hi3798C V200 with an integrated quad-core
64-bit ARM Cortex A53 processor and high performance Mali T720 GPU,
making it capable of running any commercial set-top solution based on
Linux or Android. Its high performance specification also supports a
premium user experience with up to H.265 HEVC decoding of 4K video at
60 frames per second.

SOC  Hisilicon Hi3798CV200
CPU  Quad-core ARM Cortex-A53 64 bit
DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
USB  Two USB 2.0 ports One USB 3.0 ports
CONSOLE  USB-micro port for console support
ETHERNET  1 GBe Ethernet
PCIE  One PCIe 2.0 interfaces
JTAG  8-Pin JTAG
EXPANSION INTERFACE  Linaro 96Boards Low Speed Expansion slot
DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor
WIFI  802.11AC 2*2 with Bluetooth
CONNECTORS  One connector for Smart Card One connector for TSI

The platform boot sequence is as follows:
    l-loader --> arm_trusted_firmware --> u-boot

Rep...
      e35d0edb
    • davidcunado-arm's avatar
      Merge pull request #1027 from vchong/960_bl32_optee_support · 37debcc6
      davidcunado-arm authored 
      hikey960 updates
      37debcc6
    • Isla Mitchell's avatar
      Fix order of remaining platform #includes · ee1ebbd1
      Isla Mitchell authored 
      

This fix modifies the order of system includes to meet the ARM TF coding
standard. There are some exceptions to this change in order to retain
header groupings and where there are headers within #if statements.

Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404
Signed-off-by: default avatarIsla Mitchell <isla.mitchell@arm.com>
      ee1ebbd1
    • Isla Mitchell's avatar
      Fix order of ARM platform #includes · 4adb10c1
      Isla Mitchell authored 
      

This fix modifies the order of #includes in ARM standard platforms
to meet the ARM TF coding standard.

Change-Id: Ide19aad6233babda4eea2d17d49e523645fed1b2
Signed-off-by: default avatarIsla Mitchell <isla.mitchell@arm.com>
      4adb10c1
  7. 12 Jul, 2017 8 commits
  9. 11 Jul, 2017 1 commit
  11. 10 Jul, 2017 4 commits
  13. 07 Jul, 2017 3 commits
  15. 06 Jul, 2017 7 commits
  17. 05 Jul, 2017 4 commits
  19. 02 Jul, 2017 1 commit
  21. 30 Jun, 2017 1 commit
    • Caesar Wang's avatar
      rockchip/rk3399: fixes the typo and the WARNINGS during suspend/resume · c3710ee7
      Caesar Wang authored 
      

This patch fixes the two things as follows:

1) rk3399_flash_l2_b" seems to be a typo. That's "flush", not "flash".

2) fixes the warnings log.
We always hit the warnings thing during the suspend, as below log:
..
[   51.022334] CPU5: shutdown
[   51.025069] psci: CPU5 killed.
INFO:    sdram_params->ddr_freq = 928000000
WARNING: rk3399_flash_l2_b:reg 28830380,wait

When the L2 completes the clean and invalidate sequence, it asserts the
L2FLUSHDONE signal. The SoC can now deassert L2FLUSHREQ signal and then
the L2 deasserts L2FLUSHDONE.

Then, a loop without a delay isn't really great to measure time. We should
probably add a udelay(10) or so in there and then maybe replace the WARN()
after the loop. In the actual tests, the L2 cache will take ~4ms by
default for big cluster.

In the real world that give 10ms for the enough margin, like the
ddr/cpu/cci frequency and other factors that will affect it.

Change-Id: I55788c897be232bf72e8c7b0e10cf9b06f7aa50d
Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
      c3710ee7
  23. 29 Jun, 2017 2 commits